Chung F Han from 1355 Tomlee Dr, Berkeley, CA 94702, age 92

Us Patents

Techniques And Configurations For Recessed Semiconductor Substrates
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US Patent:

20110186960, Aug 4, 2011
Filed:

Jan 14, 2011
Appl. No.:

13/007059
Inventors:

Albert Wu - Palo Alto CA, US
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Premont CA, US
International Classification:

H01L 27/04
H01L 23/488
H01L 21/60
H01L 21/98
US Classification:

257508, 257738, 438108, 257E21506, 257E21705, 257E2701, 257E23023
Abstract:

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

Recessed Semiconductor Substrates And Associated Techniques
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US Patent:

20110186992, Aug 4, 2011
Filed:

Jan 28, 2011
Appl. No.:

13/015988
Inventors:

Albert Wu - Palo Alto CA, US
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US
International Classification:

H01L 23/48
H01L 21/56
US Classification:

257737, 438108, 257774, 257E2301, 257E23011, 257E21502
Abstract:

Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Recessed Semiconductor Substrates
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US Patent:

20110186998, Aug 4, 2011
Filed:

Jan 24, 2011
Appl. No.:

13/012644
Inventors:

Albert Wu - Palo Alto CA, US
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US
International Classification:

H01L 23/48
H01L 21/50
US Classification:

257738, 438108, 257E23011, 257E21499, 257774, 257E23023
Abstract:

Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Power/Ground Layout For Chips
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US Patent:

20120098127, Apr 26, 2012
Filed:

Oct 19, 2011
Appl. No.:

13/277140
Inventors:

Sehat Sutardja - Los Altos Hills CA, US
Chung Chyung Han - San Jose CA, US
Weidan Li - San Jose CA, US
Shuhua Yu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US
Albert Wu - Palo Alto CA, US
International Classification:

H01L 23/498
H01L 21/50
US Classification:

257737, 438107, 438123, 257E21499, 257E23068
Abstract:

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Structure For Controlling Threshold Voltage Of Mosfet
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US Patent:

57930880, Aug 11, 1998
Filed:

Jun 18, 1996
Appl. No.:

8/664440
Inventors:

Jeong Yeol Choi - Fremont CA
Chung-Jen Chien - Saratoga CA
Chung Chyung Han - San Jose CA
Chuen-Der Lien - Los Altos Hills CA
Assignee:

Integrated Device Technology, Inc. - Santa Clara CA
International Classification:

H01L 2976
H01L 2994
H01L 31062
H01L 31113
US Classification:

257408
Abstract:

A method and structure for controlling the threshold voltage of a MOSFET is provided. The method compensates for the edge effect associated with prior art halo implants by providing an edge threshold voltage implant (the VT implant) which passes impurities through dielectric spacers, through the underlying source/drain regions and into the edges of the halo regions which lie in the channel. The VT implant reduces junction capacitance and does not degrade punchthrough voltage.

Power/Ground Layout For Chips
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US Patent:

20150155202, Jun 4, 2015
Filed:

Feb 3, 2015
Appl. No.:

14/613157
Inventors:

- St. Michael, BB
Chung Chyung Han - San Jose CA, US
Weidan Li - San Jose CA, US
Shuhua Yu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US
Albert Wu - Palo Alto CA, US
International Classification:

H01L 21/768
H01L 25/00
H01L 23/00
Abstract:

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Techniques And Configurations For Recessed Semiconductor Substrates
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US Patent:

20140124961, May 8, 2014
Filed:

Jan 13, 2014
Appl. No.:

14/153892
Inventors:

- St. Michael, BB
Roawen Chen - Monte Sereno CA, US
Chung Chyung Han - San Jose CA, US
Shiann-Ming Liou - Campbell CA, US
Chien-Chuan Wei - Los Gatos CA, US
Runzi Chang - San Jose CA, US
Scott Wu - San Jose CA, US
Chuan-Cheng Cheng - Fremont CA, US
Assignee:

Marvell World Trade Ltd. - St. Michael
International Classification:

H01L 25/04
US Classification:

257777
Abstract:

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.