Clark L Williams

US Patent:

61186902, Sep 12, 2000

Filed:

Nov 27, 1995

Appl. No.:

8/563152

Inventors:

Ching-Lin Jiang - Dallas TX
Clark R. Williams - Plano TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

G11C 11419

US Classification:

365156

Abstract:

A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

US Patent:

49124358, Mar 27, 1990

Filed:

Sep 7, 1989

Appl. No.:

7/404943

Inventors:

Clark R. Williams - Plano TX
Ching-Lin Jiang - Dallas TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H03B 536

US Classification:

331 75

Abstract:

A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

US Patent:

52672220, Nov 30, 1993

Filed:

Jun 18, 1991

Appl. No.:

7/717215

Inventors:

Clark R. Williams - Plano TX
William J. Podkowa - Plano TX

Assignee:

Dallas Semiconductor Corp. - Dallas TX

International Classification:

G04C 1500

US Classification:

368155

Abstract:

A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

US Patent:

51500795, Sep 22, 1992

Filed:

Jun 18, 1991

Appl. No.:

7/717238

Inventors:

Clark R. Williams - Plano TX
Ching-Lin Jiang - Dallas TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H03B 500

US Classification:

331 75

Abstract:

A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

US Patent:

54870968, Jan 23, 1996

Filed:

Jun 14, 1994

Appl. No.:

8/259421

Inventors:

Ronald W. Pearson - Denton TX
Kevin E. Deierling - Dallas TX
Clark R. Williams - Plano TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

G06M 302

US Classification:

377 15

Abstract:

An integrated circuit which includes not only a real time clock, but also an elapsed time counter, and a third counter. The elapsed time counter measures the total number of seconds during which a system has been powered up. The third counter is a "cycle counter," which measures the number of times a power cycle (power-up and power-down) has occurred. Thus, by reading the cycle counter and the elapsed time indicator, the general power history of a system can readily be determined, even if the system itself has totally failed. This integrated circuit is battery backed, and is advantageously combined with a system for which power history must be maintained.

US Patent:

39861996, Oct 12, 1976

Filed:

Feb 19, 1974

Appl. No.:

5/443585

Inventors:

Clark R. Williams - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702
H01L 2972
H01L 2710
H01L 2704

US Classification:

357 46

Abstract:

An electronic timekeeping system is implemented in bipolar integrated circuit technology for displaying time by way of a digital display. The bipolar circuitry is implemented utilizing integrated injection logic and the countdown chain utilizes flip-flops having geometries configured to effect power grading. That is, the emitter geometry of the PNP injector is selectively varied so as to vary the injection base drive current.

US Patent:

51756994, Dec 29, 1992

Filed:

Oct 28, 1988

Appl. No.:

7/264233

Inventors:

William J. Podkowa - Plano TX
Clark R. Williams - Plano TX

Assignee:

Dallas Semiconductor Corp. - Dallas TX

International Classification:

G06F 1520
G06F 1300

US Classification:

364569

Abstract:

An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.

US Patent:

41143663, Sep 19, 1978

Filed:

Aug 2, 1976

Appl. No.:

5/710524

Inventors:

Karl H. Renner - Dallas TX
Clark Russell Williams - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G04B 1930
G04C 300
H05B 3702
H05B 3904

US Classification:

58 50R

Abstract:

A digital light-sensing control system for use in light sensitive equipment, such as a digital watch or a camera, is comprised of light sensor means such as a photo resistor, a digital brightness detector, and brightness control logic. The light sensor means produces analog signals which vary with ambient light intensity. The digital brightness detector selectively digitizes the analog signals to generate digital brightness signals. The brightness control logic generates system control signals in response to the digital brightness signals. Several embodiments of the digital brightness detector and the brightness control logic are disclosed. Each embodiment is capable of being integrated on a single semiconductor substrate.