Clay C Johnson

US Patent:

6664808, Dec 16, 2003

Filed:

Aug 7, 2001

Appl. No.:

09/924365

Inventors:

Zhi-Min Ling - Cupertino CA
Jae Cho - Sunnyvale CA
Robert W. Wells - Cupertino CA
Clay S. Johnson - San Jose CA
Shelly G. Davis - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 10

Abstract:

FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.