Clay Smith

US Patent:

6338025, Jan 8, 2002

Filed:

Oct 8, 1998

Appl. No.:

09/168589

Inventors:

Michael Alexander Bowen - Poughkeepsie NY
Byron Lee Krauter - Austin TX
Steven Arthur Schmidt - Leander TX
Clay Chip Smith - Austin TX
Amy May Tuvell - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1900

US Classification:

702 60, 702 52, 702117, 716 4, 716 6, 703 14, 703 15, 703 18, 703 19

Abstract:

An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and âone cycle per cycleâ circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

US Patent:

59915218, Nov 23, 1999

Filed:

Mar 31, 1997

Appl. No.:

8/829578

Inventors:

Carol Ivash Gabele - Austin TX
Stephen Thomas Quay - Austin TX
Clay Chip Smith - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

39550005

Abstract:

An integrated-circuit design is provided which is represented by a hierarchial data structure. In accordance with the method and system of the present invention, an integrated-circuit design which includes at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data. For an open circuit connection within the child circuit, a determination is made as to whether or not the open circuit connection is permissible. In response to a determination that the open circuit connection is permissible, another determination is made as to whether or not the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit. In response to a determination that the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit, the set of child circuit level data is integrated into the set of parent circuit level data. Finally, a determination is made as to whether or not the open circuit connection is closed within the integrated set of parent circuit level data.

US Patent:

20170277010, Sep 28, 2017

Filed:

Mar 21, 2017

Appl. No.:

15/464884

Inventors:

- Farmington Hills MI, US
Clay Smith - Bloomfield Hills MI, US

International Classification:

G02F 1/167
G09F 23/00
G09F 13/12
G02F 1/01

Abstract:

A graphic display apparatus including a substrate including a first major surface and a second major surface, the substrate configured to transmit light when the graphic display apparatus is in a transmissive mode and reflect light when the graphic display apparatus is in a reflective mode; a reflective layer positioned on the first major surface of the substrate; a tint layer positioned on the second major surface; a diffuser layer including an image that is positioned on the tint layer such that the diffuser layer and the substrate sandwich the tint layer; and a light source located proximate the diffuser layer such that the light source and the diffuser layer sandwich the image, wherein, when the graphic display apparatus is in the transmissive mode, the light source illuminates the image such that the image is viewable from the first major surface of the substrate, and when the graphic display apparatus is in the reflective mode, the image is not illuminated by the light source and is not viewable from the first major surface of the substrate.