Cliff Reader

US Patent:

61920738, Feb 20, 2001

Filed:

Aug 19, 1996

Appl. No.:

8/699382

Inventors:

Cliff Reader - Saratoga CA
Jae Cheol Son - Cupertino CA
Amjad Qureshi - San Jose CA
Le Nguyen - Monte Sereno CA
Mark Frederiksen - Schaumburg IL
Tim Lu - Schaumburg IL

Assignee:

Samsung Electronics Co., Ltd. - Seoul

International Classification:

H04N 718

US Classification:

375240

Abstract:

A computer system includes three processors capable to operate concurrently--a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory.

US Patent:

58451129, Dec 1, 1998

Filed:

Mar 6, 1997

Appl. No.:

8/812774

Inventors:

Le Trong Nguyen - Monte Sereno CA
Heonchul Park - Cupertino CA
Cliff Reader - Saratoga CA
Yoon Lee - San Jose CA

Assignee:

Samsung Electronics Co., Ltd. - Seoul

International Classification:

G06F 9302

US Classification:

395562

Abstract:

An extension to existent vector instruction sets is presented in a form of new vector instructions which perform operations specialized for efficient digital video compression and decompression. A processor is designed to implement the arithmetic operation of each of these instructions in a single clock cycle, and some of the present instructions perform arithmetic operations selectively and directly on elements of the same registers.