Colin Christopher Sharp

US Patent:

6850244, Feb 1, 2005

Filed:

Jan 11, 2001

Appl. No.:

09/759789

Inventors:

Aaftab Munshi - Los Gatos CA, US
Colin Sharp - San Jose CA, US

Assignee:

Micron Techology, Inc. - Boise ID

International Classification:

G06T 1500

US Classification:

345584

Abstract:

A method and system for providing surface texture in a graphics image rendered by a graphics processing system. Color values of a pixel having a normal vector normal to a surface in which the pixel is located are calculated based on a perturbed normal vector. The perturbed normal vector is displaced from the normal vector by a displacement equal to the sum of a first vector tangent to the surface at the location of the pixel scaled by a first scale factor and a first displacement value, and a second vector tangent to the surface at the location of the pixel and scaled by a second scale factor and a second displacement value, the second vector perpendicular to the first vector. The displacement values are representative of partial derivatives of a function defining a texture applied to the surface and the scale factors are used to scale the magnitude of the resulting perturbed normal. The color value for the pixel being rendered will be based on the perturbed normal vector instead of the normal vector.

US Patent:

7287092, Oct 23, 2007

Filed:

Aug 11, 2003

Appl. No.:

10/639810

Inventors:

Colin C. Sharp - Santa Cruz CA, US

International Classification:

G06F 15/16
H04L 12/56

US Classification:

709245, 37039532, 707 3, 709250

Abstract:

A TCP/IP offload network interface device (NID) receives packets from a plurality of clients and generates, from the socket address of each such packet, a hash value. Each hash value identifies one of a plurality of hash buckets maintained on the NID. In a file server, certain socket address bits of the packets are low entropy bits in that they tend to be the same, regardless of which client sent the packet. Others of the socket address bits are high entropy bits. The hash function employed is such that the hash values resulting from the changing values of the high entropy bits are substantially evenly distributed among the plurality of hash buckets. In a fast-path, the NID uses a first hash function to identify TCBs on the NID. In a slow-path, the NID generates a second hash using a second hash function and a host stack uses the second hash.

US Patent:

7496689, Feb 24, 2009

Filed:

Apr 22, 2003

Appl. No.:

10/420364

Inventors:

Colin C. Sharp - Santa Cruz CA, US
Clive M. Philbrick - San Jose CA, US
Daryl D. Starr - Milpitas CA, US
Stephen E. J. Blightman - San Jose CA, US

Assignee:

Alacritech, Inc. - San Jose CA

International Classification:

G06F 15/173
G06F 15/16
G06F 12/00
H04L 15/00

US Classification:

709250, 709238, 711108, 370463

Abstract:

A TCP/IP offload network interface device (NID) is integrated with a processing device that executes a stack. The TCP/IP offload NID can either be a full TCP/IP offload device or a partial TCP/IP offload device. Common types of packets are processed by the NID in a fast-path such that the stack is offloaded of TCP and IP protocol processing tasks. A hash is made from the packet header and is pushed onto a queue. The hash is later popped off the queue and is used to identify an associated TCB number from a hash table. A mechanism caches hash buckets in SRAM and stores other hash buckets in DRAM. An “IN SRAM CAM” is used to determine whether the TCB associated with the identified TCB number is cached in SRAM or whether it must be moved from DRAM into the SRAM cache. A lock table and a “lock table CAM” mechanism is disclosed that facilitates multiple processors working on the protocol processing of a single packet.

US Patent:

8248939, Aug 21, 2012

Filed:

Oct 11, 2005

Appl. No.:

11/249006

Inventors:

Peter K. Craft - San Francisco CA, US
Joseph L. Gervais - Fremont CA, US
Colin C. Sharp - Half Moon Bay CA, US

Assignee:

Alacritech, Inc. - San Jose CA

International Classification:

G01R 31/08

US Classification:

370235, 370469

Abstract:

In one embodiment, a system for communicating over a network is disclosed, the system comprising: a processor running a protocol processing stack to control a TCP connection; a first offload engine that receives control of the TCP connection from the stack to perform a first task corresponding to the TCP connection; and a second offload engine that receives control of the TCP connection from the first offload engine to perform a second task corresponding to the TCP connection. For example, the first offload engine can be protocol software such as an intermediate driver that can handle tasks such as teaming and/or reassembly of out-of-order data segments. As another example, the second offload engine can be a network interface card that provides hardware that accelerates data transfer.

US Patent:

20080040519, Feb 14, 2008

Filed:

May 1, 2007

Appl. No.:

11/799720

Inventors:

Daryl Starr - Milpitas CA, US
Clive Philbrick - San Jose CA, US
Colin Sharp - Cardiff CA, US

International Classification:

G06F 3/00

US Classification:

710039000

Abstract:

A 10 Gb/s network interface device offloads TCP/IP datapath functions. Frames without IP datagrams are processed as with a non-offload NIC. Receive frames are filtered, then transferred to preallocated receive buffers within host memory. Outbound frames are retrieved from host memory, then transmitted. Frames with IP datagrams without TCP segments are transmitted without any protocol offload, but received frames are parsed and checked for protocol errors, including checksum accumulation for UDP segments. Receive frames without datagram errors are passed to the host and error frames are dumped. Frames with Tcp segments are parsed and error-checked. Hardware checking is performed for ownership of the socket state. TCP/IP frames which fail the ownership test are passed to the host system with a parsing summary. TCP/IP frames which pass the ownership test are processed by a finite state machine implemented by the CPU. TCP/IP frames for non-owned sockets are supported with checksum accumulation/insertion.

US Patent:

20120069029, Mar 22, 2012

Filed:

Sep 16, 2011

Appl. No.:

13/235236

Inventors:

Alexei V. Bourd - San Diego CA, US
Colin Christopher Sharp - Cardiff CA, US
David Rigel Garcia Garcia - Toronto, CA
Chihong Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 15/16

US Classification:

345502

Abstract:

This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

US Patent:

20120069035, Mar 22, 2012

Filed:

Sep 16, 2011

Appl. No.:

13/235266

Inventors:

Alexei V. Bourd - San Diego CA, US
Colin Christopher Sharp - Cardiff CA, US
David Rigel Garcia Garcia - Toronto, CA
Chihong Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 15/167

US Classification:

345541, 345557

Abstract:

This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

US Patent:

20120185671, Jul 19, 2012

Filed:

Jan 14, 2011

Appl. No.:

13/007333

Inventors:

Alexei V. Bourd - San Diego CA, US
Andrew Gruber - Arlington MA, US
Aleksandra L. Krstic - San Diego CA, US
Robert J. Simpson - Espoo, FI
Colin Sharp - Cardiff CA, US
Chun Yu - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

G06F 9/38

US Classification:

712 27, 712E09071

Abstract:

This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.