Colyn S Case

US Patent:

7386697, Jun 10, 2008

Filed:

Mar 10, 2005

Appl. No.:

11/077662

Inventors:

Colyn S. Case - Hyde Park VT, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711171, 711209, 710 9

Abstract:

In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. The clusters are dynamically created from a fragmented pool of physical addresses as new virtual address mappings are requested by consumers of the virtual memory space.

US Patent:

7415575, Aug 19, 2008

Filed:

Dec 8, 2005

Appl. No.:

11/298256

Inventors:

Peter C. Tong - Cupertino CA, US
Colyn S. Case - Hyde Park VT, US

Assignee:

NVIDIA, Corporation - Santa Clara CA

International Classification:

G06F 12/12

US Classification:

711133, 711159, 711129

Abstract:

A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of replacing entries, at least of the clients is restricted, and when a cache miss results from a request by the restricted client, the entry to be replaced is selected from a fixed subset of the cache entries. When a cache misses results from a request by any client other than the restricted client, any cache entry, including a restricted entry, can be selected to be replaced.

US Patent:

7469311, Dec 23, 2008

Filed:

Dec 19, 2006

Appl. No.:

11/613150

Inventors:

William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 13/40

US Classification:

710307, 710 29

Abstract:

A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

US Patent:

7526593, Apr 28, 2009

Filed:

Oct 3, 2006

Appl. No.:

11/538399

Inventors:

Manas Mandal - Palo Alto CA, US
William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
Ashish Kishen Kaul - Santa Clara CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 13/00

US Classification:

710310, 710 35, 370473, 370474, 370393, 370465

Abstract:

Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.

US Patent:

7624221, Nov 24, 2009

Filed:

Jul 28, 2006

Appl. No.:

11/460960

Inventors:

Colyn S. Case - Hyde Park VT, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 13/40

US Classification:

710310, 710 18

Abstract:

Optimization logic that optimizes a stream of requests being transmitted onto a link by a link interface unit can be enabled or disabled based on a performance metric that represents a measure of the degree to which a response to a request is likely to be slowed due to congestion, propagation delays, or other bottlenecks in the system. For example, the performance metric can be based on a measured level of link activity due to requests from the transmitting device and/or a prediction as to behavior (e. g. , access time) of the target device that receives the stream of requests. The control logic advantageously does not require extra signals to be carried on the bus.

US Patent:

7664905, Feb 16, 2010

Filed:

Nov 3, 2006

Appl. No.:

11/592540

Inventors:

David A. Jarosh - Santa Clara CA, US
Sonny S. Yeoh - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
John H. Edmondson - Arlington MA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 13/14

US Classification:

711 5, 711154, 711158, 711165

Abstract:

In some applications, such as video motion compression processing for example, a request pattern or “stream” of requests for accesses to memory (e. g. , DRAM) may have, over a large number of requests, a relatively small number of requests to the same page. Due to the small number of requests to the same page, conventionally sorting to aggregate page hits may not be very effective. Reordering the stream can be used to “bury” or “hide” much of the necessary precharge/activate time, which can have a highly positive impact on overall throughput. For example, separating accesses to different rows of the same bank by at least a predetermined number of clocks can effectively hide the overhead involved in precharging/activating the rows.

US Patent:

7788439, Aug 31, 2010

Filed:

Oct 16, 2008

Appl. No.:

12/252525

Inventors:

William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 13/40

US Classification:

710307, 710 29

Abstract:

A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

US Patent:

7797510, Sep 14, 2010

Filed:

Apr 30, 2008

Appl. No.:

12/112602

Inventors:

Colyn S. Case - Hyde Park VT, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711207, 345543

Abstract:

In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. The clusters are dynamically created from a fragmented pool of physical addresses as new virtual address mappings are requested by consumers of the virtual memory space.