Connie E Wong

US Patent:

6469394, Oct 22, 2002

Filed:

Jan 31, 2000

Appl. No.:

09/494756

Inventors:

Connie M. Wong - Fremont CA
Michael G. Lee - San Jose CA

Assignee:

Fujitsu Limited

International Classification:

H01L 2348

US Classification:

257780, 257778, 257789, 438108, 438612

Abstract:

Interconnect structures and methods for making interconnect structures are disclosed. A typical interconnect structure has a tapered first end portion having a first substantially planar surface and a concave surface adjacent to the first planar surface. A second end portion of the interconnect structure includes a second substantially planar surface. The second planar surface has a larger area than the first planar surface. An intermediate portion is disposed between the first end portion and the second end portion.

US Patent:

7963906, Jun 21, 2011

Filed:

Dec 30, 2010

Appl. No.:

12/982341

Inventors:

Connie C. Wong - Palo Alto CA, US
Kevin E. Loewke - Menlo Park CA, US
Barry Behr - Palo Alto CA, US
Thomas M. Baer - Palo Alto CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

A61B 17/43
A61D 7/00
C12N 5/00
C12N 5/02

US Classification:

600 33, 600 34, 600 35, 435375, 435 83

Abstract:

Methods, compositions and kits for determining the developmental potential of one or more embryos or pluripotent cells and/or the presence of chromosomal abnormalities in one or more embryos or pluripotent cells are provided. These methods, compositions and kits find use in identifying embryos and oocytes in vitro that are most useful in treating infertility in humans.

US Patent:

20110092762, Apr 21, 2011

Filed:

Aug 23, 2010

Appl. No.:

12/861571

Inventors:

Connie C. Wong - Palo Alto CA, US
Kevin E. Loewke - Menlo Park CA, US
Thomas M. Baer - Palo Alto CA, US
Barry Behr - Palo Alto CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

A61B 17/435
C12Q 1/02
C12Q 1/68
C12M 1/34
C12M 1/22

US Classification:

600 34, 435 29, 435 6, 4352883, 4353052

Abstract:

Methods, compositions and kits for determining the developmental potential of one or more embryos or pluripotent cells and/or the presence of chromosomal abnormalities in one or more embryos or pluripotent cells are provided. These methods, compositions and kits find use in identifying embryos and oocytes in vitro that are most useful in treating infertility in humans.

US Patent:

53348044, Aug 2, 1994

Filed:

Nov 17, 1992

Appl. No.:

7/977571

Inventors:

David G. Love - Pleasanton CA
Larry L. Moresco - San Carlos CA
William T. Chou - Cupertino CA
David A. Horine - Los Altos CA
Connie M. Wong - Fremont CA
Solomon I. Beilin - San Carlos CA

Assignee:

Fujitsu Limited - Kanagawa

International Classification:

H05K 0100

US Classification:

174267

Abstract:

An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one anther so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

US Patent:

55363628, Jul 16, 1996

Filed:

Feb 16, 1994

Appl. No.:

8/197232

Inventors:

David G. Love - Pleasanton CA
Larry L. Moresco - San Carlos CA
William Tai-Hua Chou - Cupertino CA
David A. Horine - Los Altos CA
Connie M. Wong - Fremont CA
Solomon I. Beilin - San Carlos CA

Assignee:

Fujitsu Limited

International Classification:

H01L 2100
B44C 122

US Classification:

1566431

Abstract:

Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures. Additionally, some of the disclosed methods comprise steps for forming fillets around the conductive post at the substrate surface.

US Patent:

57738890, Jun 30, 1998

Filed:

Sep 23, 1996

Appl. No.:

8/710840

Inventors:

David George Love - Pleasanton CA
Larry Louis Moresco - San Carlos CA
William Tai-Hua Chou - Cupertino CA
David Albert Horine - Los Altos CA
Connie Mak Wong - Fremont CA
Solomon Isaac Beilin - San Carlos CA

Assignee:

Fujitsu Limited - Kanagawa

International Classification:

H01L 2348

US Classification:

257737

Abstract:

An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprising an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a means for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one anther so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.