Corey Lee Larsen

US Patent:

6381707, Apr 30, 2002

Filed:

Apr 28, 1998

Appl. No.:

09/067347

Inventors:

Corey Larsen - Marsing ID
Richard Weber - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1100

US Classification:

714 8

Abstract:

The use of a partially defective memory array to create a non-defective memory array. In a manner transparent to the memory controller, an address decoder is used to make a large memory array look like a smaller, non-defective memory array.

US Patent:

6381708, Apr 30, 2002

Filed:

Apr 28, 1998

Appl. No.:

09/067467

Inventors:

Corey Larsen - Marsing ID
Richard Weber - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1100

US Classification:

714 8

Abstract:

The use of a partially defective memory array to create a non-defective memory array. In a manner transparent to the memory controller, an address decoder is used to make a large memory array look like a smaller, non-defective memory array.

US Patent:

6418034, Jul 9, 2002

Filed:

Nov 27, 2001

Appl. No.:

09/995936

Inventors:

Rick Weber - Boise ID
Corey Larsen - Marsing ID
James Howarth - Marsing ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H05K 114

US Classification:

361790, 361784, 361785, 361803, 439 44, 439 69, 439 74, 22818021, 22818022

Abstract:

A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electronically and mechanically interconnected with another board.

US Patent:

6484299, Nov 19, 2002

Filed:

Jul 7, 2000

Appl. No.:

09/612155

Inventors:

Corey L. Larsen - Marsing ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1750

US Classification:

716 6, 716 4, 716 5, 716 15

Abstract:

A method and apparatus for compensating propagation delay in an electronic system relating to corresponding signals becoming skewed by variations in the dielectric materials over which the respective, corresponding signals travel. Compensation for the propagation delay is done by selecting printed circuit boards which each have one side comprised of a dielectric substrate material exhibiting a first dielectric constant and another side comprised of a dielectric substrate material exhibiting a second dielectric constant. By transmitting each of the corresponding signals across a side of a printed circuit board with a first dielectric constant and a side with a second dielectric constant, the signals are each delayed substantially the same by the effects of the dielectric constant, reducing the skew to zero. In specific application, the printed circuit boards are most easily matched by selecting printed circuit boards from a common printed circuit board panel or array. The invention has particular application in source synchronous device systems such as an RDRAMÂ system.

US Patent:

6578157, Jun 10, 2003

Filed:

Mar 6, 2000

Appl. No.:

09/519641

Inventors:

Richard R. Weber - Boise ID
Corey L. Larsen - Marsing ID
James J. Howarth - Marsing ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1100

US Classification:

714 8, 714 7, 714710

Abstract:

A memory module using a plurality of partially defective RDRAM devices in combination to simulate a single, fully operational RDRAM device. Multiple partially defective RDRAM devices are configured to simulate a fully operational RDRAM device by taking advantage of the manner in which defective cells are localized on each RDRAM device.

US Patent:

6621748, Sep 16, 2003

Filed:

Aug 21, 2001

Appl. No.:

09/938461

Inventors:

Richard Weber - Boise ID
Corey Larsen - Marsing ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

365200, 36523003, 714 1

Abstract:

A memory module is disclosed which is constructed using partially defective synchronous memory devices, such as SDRAM components. The multiple partially defective SDRAM components are configured to provide a reliable and nondefective memory module that takes advantage of the manner in which defective cells are localized on each SDRAM component.

US Patent:

6810492, Oct 26, 2004

Filed:

May 6, 2003

Appl. No.:

10/430851

Inventors:

Richard R. Weber - Boise ID
Corey L. Larsen - Marsing ID
James J. Howarth - Marsing ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1100

US Classification:

714 8, 714 7, 714710

Abstract:

A memory module using a plurality of partially defective RDRAM devices in combination to simulate a single, fully operational RDRAM device. Multiple, partially defective RDRAM devices are configured to simulate a fully operational RDRAM device by taking advantage of the manner in which defective cells are localized on each RDRAM device.

US Patent:

6817002, Nov 9, 2004

Filed:

Aug 20, 2002

Appl. No.:

10/224102

Inventors:

Corey L. Larsen - Marsing ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1750

US Classification:

716 6, 716 4, 716 5

Abstract:

A method and apparatus are provided for compensating propagation delay in an electronic system relating to corresponding signals becoming skewed by variations in the dielectric materials over which the respective, corresponding signals travel. Compensation for the propagation delay is done by selecting printed circuit boards which each have one side comprised of a dielectric substrate material exhibiting a first dielectric constant and another side comprised of a dielectric substrate material exhibiting a second dielectric constant. By transmitting each of the corresponding signals across a side of a printed circuit board with a first dielectric constant and a side with a second dielectric constant, the signals are each delayed substantially the same by the effects of the dielectric constant, reducing the skew to zero. In specific application, the printed circuit boards are most easily matched by selecting printed circuit boards from a common printed circuit board panel or array.