Craig D Davis

US Patent:

54205450, May 30, 1995

Filed:

Mar 16, 1994

Appl. No.:

8/213935

Inventors:

Craig M. Davis - Puyallup WA
David A. Byrd - Puyallup WA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L 7107
H03L 718

US Classification:

331 17

Abstract:

A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time. The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison. The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO). The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator. The feedback converter is another programmable frequency divider which, in accordance with a feedback proportionality factor dynamically determined by a feedback control signal, reduces the frequency of the VCO feedback signal frequency used by the phase comparator.

US Patent:

59072539, May 25, 1999

Filed:

Nov 24, 1997

Appl. No.:

8/977308

Inventors:

Craig Davis - Puyallup WA
Jeff Huard - Puyallup WA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L 706

US Classification:

327156

Abstract:

A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals for the feedback signal are: increased when small fractional divisors (1/2) causing a leading phase relationship are sensed; and decreased when small fractional divisors (1/2) causing a lagging phase relationship are sensed.

US Patent:

51666413, Nov 24, 1992

Filed:

Mar 17, 1992

Appl. No.:

7/852639

Inventors:

Craig M. Davis - Puyallup WA
David A. Byrd - Puyallup WA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L 7085

US Classification:

331 1A

Abstract:

A phase-locked loop having automatic internal phase offset calibration includes a voltage-controlled oscillator circuit for generating a recovered data signal in response to an error signal. A phase detector determines the phase difference between the recovered data signal and a reference data signal. The phase-locked loop further includes a charge pump circuit, coupled to the phase detector, for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators being interconnected to facilitate generation of the error signal. The phase-locked loop is designed to alternate between operation in phase correction and phase calibration cycles. In each phase correction cycle an error signal is synthesized as described above on the basis of the most recent phase comparison.

US Patent:

50897233, Feb 18, 1992

Filed:

Nov 15, 1990

Appl. No.:

7/613291

Inventors:

Craig M. Davis - Puyallup WA
Richard R. Rasmussen - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 19094
H03K 190175

US Classification:

307451

Abstract:

The present invention provides a CMOS output buffer with ECL output characteristics that allows the outputs to be terminated in any manner desired and which is not limited by the op amp settling time. The buffer establishes a bus internally for the VOH and VOL levels and then switches between the buses using transmission gates. In the disclosed embodiment of the invention, the op amp's feedback path includes a P-channel device which is either identical to or, to conserve power, a carefully scaled down equivalent of the P-channel output device.

US Patent:

53941144, Feb 28, 1995

Filed:

Jun 23, 1993

Appl. No.:

8/081955

Inventors:

Craig M. Davis - Puyallup WA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 301
H03L 706

US Classification:

331 1A

Abstract:

Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.