Craig R Hansen

US Patent:

6378060, Apr 23, 2002

Filed:

Feb 11, 2000

Appl. No.:

09/502856

Inventors:

Craig Hansen - Los Altos CA
Bruce Bateman - Fremont CA
John Moussouris - Palo Alto CA

Assignee:

Microunity Systems Engineering, Inc. - Santa Clara CA

International Classification:

G06F 1300

US Classification:

712 32, 712 28, 712 23, 712 34, 711209

Abstract:

The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2 -bit (e. g. 256-bit) input source word to be switched into any bit position of a 2 -bit (e. g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2 -bit output destination word. The cross-bar circuit includes: (1) a switch circuit which includes 2 2 :1 multiplexor circuits, where each of the 2 :1 multiplexor circuits (a) has a unique n-bit (e. g. 8-bit) index input, one disable input, and a 2 -bit wide source input, (b) receives (i) an n-bit index at the n-bit index input, (ii) a disable bit at the disable input, and (iii) the 2 -bit input source word at the 2 -bit wide source input, and (c) decodes the n-bit index either (i) to select and output as an output destination bit one bit from the 2 -bit input source word if the disable bit has a logic low value or (ii) outputs a logic low as the output destination bit if the disable bit has a logic high value; (2) a cache memory that (a) has 2 cache datapath inputs and 2 cache index inputs, (b) receives (i) the datapath information on the 2 cache datapath inputs and (ii) 2 n-bit indexes on the 2 cache index inputs, (c) provides a first set of the n-bit indexes for the switch circuit, and (d) includes a small tightly coupled memory array that stores p (e. g. eight) entries of 2 n-bit indexes for the switch circuit, where the cache memory is logically coupled to the switch circuit; and (3) a control circuit that (a) has a plurality (e. g.

US Patent:

6427190, Jul 30, 2002

Filed:

May 12, 2000

Appl. No.:

09/570402

Inventors:

Craig C. Hansen - Los Altos CA

Assignee:

MicroUnity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 1202

US Classification:

711129, 711123, 711119, 711125, 711131, 711173

Abstract:

A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

US Patent:

6584482, Jun 24, 2003

Filed:

Aug 19, 1999

Appl. No.:

09/377182

Inventors:

Craig C. Hansen - Los Altos CA
Henry Massalin - Sunnyvale CA

Assignee:

Microunity Systems Engineering, Inc. - Santa Clara CA

International Classification:

G06F 1715

US Classification:

708523, 708420, 708501, 708603, 712221

Abstract:

A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

US Patent:

6643765, Nov 4, 2003

Filed:

Mar 24, 2000

Appl. No.:

09/534745

Inventors:

Craig Hansen - Los Altos CA
John Moussouris - Palo Alto CA

Assignee:

Microunity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 1500

US Classification:

712 32, 712208, 712 28

Abstract:

A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.

US Patent:

6725356, Apr 20, 2004

Filed:

Aug 2, 2001

Appl. No.:

09/922319

Inventors:

Craig Hansen - Los Altos CA
John Moussouris - Palo Alto CA

Assignee:

MicroUnity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 1500

US Classification:

712210, 712 28, 712 24, 712 32, 712208

Abstract:

The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.

US Patent:

RE39500, Feb 27, 2007

Filed:

Jul 29, 2004

Appl. No.:

10/901482

Inventors:

Craig C. Hansen - Los Altos CA, US

Assignee:

MicroUnity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 12/02

US Classification:

711203, 711202, 711205, 711118, 711170

Abstract:

A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

US Patent:

7213131, May 1, 2007

Filed:

Jan 15, 2004

Appl. No.:

10/757524

Inventors:

Craig Hansen - Los Altos CA, US
John Moussouris - Palo Alto CA, US

Assignee:

Microunity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 7/00

US Classification:

712220

Abstract:

A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

US Patent:

7216217, May 8, 2007

Filed:

Aug 25, 2003

Appl. No.:

10/646787

Inventors:

Craig Hansen - Los Altos CA, US
John Moussouris - Palo Alto CA, US

Assignee:

Microunity Systems Engineering, Inc. - Santa Clara CA

International Classification:

G06F 15/16
G06F 15/00

US Classification:

712221, 708523

Abstract:

A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.