Craig N Lambert

US Patent:

7543163, Jun 2, 2009

Filed:

Jan 4, 2006

Appl. No.:

11/326104

Inventors:

Kent Kernahan - Cupertino CA, US
John Carl Thomas - Sunnyvale CA, US
Craig Norman Lambert - San Jose CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32

US Classification:

713300, 713320, 713322, 713340

Abstract:

A synchronous control system includes a logic controller (e. g. , microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold.

US Patent:

7574321, Aug 11, 2009

Filed:

Oct 11, 2006

Appl. No.:

11/548283

Inventors:

Kent Kernahan - Cupertino CA, US
Craig Norman Lambert - San Jose CA, US
Sorin Andrei Spanoche - Santa Clara CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

G06F 19/00
G01K 17/00

US Classification:

702179, 702136, 702187, 702188, 713300

Abstract:

Electrical components which substantially dissipate the power provided them in the form of heat will change temperature in response to self heating, heat transfer to their surroundings, and heat transferred from one component to another. A method is disclosed for calculating the temperature of a component(s) using a thermal model. In one embodiment the power dissipation of each component is controlled to limit the temperature of the component. In one embodiment the temperature of a component is modified by changing the power dissipation of another component. In some embodiments the power dissipation of a component is modified by modifying its performance. In another embodiment power dissipation is modified by selecting one or more programs for modified execution.

US Patent:

7908508, Mar 15, 2011

Filed:

May 16, 2009

Appl. No.:

12/467275

Inventors:

Kent Kernahan - Cupertino CA, US
John Carl Thomas - Sunnyvale CA, US
Craig Norman Lambert - San Jose CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32
G06F 5/06

US Classification:

713600, 713300, 713320, 713322, 713500, 713501

Abstract:

A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost.

US Patent:

20080116861, May 22, 2008

Filed:

Jan 2, 2007

Appl. No.:

11/618942

Inventors:

KENT KERNAHAN - CUPERTINO CA, US
MILTON D. RIBEIRO - LOS ALTOS CA, US
DONGSHENG ZHOU - SAN JOSE CA, US
SORIN ANDREI SPANOCHE - SANTA CLARA CA, US
CRAIG NORMAN LAMBERT - SAN JOSE CA, US
MICHAEL W. CALDWELL - SANTA CLARA CA, US
JINGQUAN CHEN - SAN JOSE CA, US

International Classification:

G05F 1/577
G05F 1/00
H03H 11/26

US Classification:

323267, 323265, 327276

Abstract:

The voltage applied to an integrated circuit is controlled by a temporal process monitor formed as part of the integrated circuit. The temporal process monitor includes a voltage controlled oscillator for producing a first output signal having a first period. A comparator compares the first period to one or more reference values. Should the first period be greater than a first selected reference value the comparator sends a signal to increase the voltage being supplied to the integrated circuit. Should the first period be less than a second selected reference value, the comparator sends a signal to decrease the voltage applied to the integrated circuit. In some embodiments a scaling circuit is provided for producing a second output signal having a second period different from (typically but not necessarily longer than) the first period. By placing the temporal process monitor on an integrated circuit chip, process variations and environmental factors which affect the performance of the integrated circuit can be automatically compensated so that the integrated circuit performs within specifications. Two or more temporal process monitors can be placed on a single integrated circuit chip or on different integrated circuit chips and the longest period produced by the temporal process monitors can be used to control the voltage supplied to all the sections of the integrated circuit chip associated with the temporal process monitors or to all the integrated circuit chips associated with the temporal process monitors.

US Patent:

20080116964, May 22, 2008

Filed:

Nov 22, 2006

Appl. No.:

11/604165

Inventors:

Kent Kernahan - Cupertino CA, US
Milton D. Ribeiro - Los Altos CA, US
Dongsheng Zhou - San Jose CA, US
Sorin Andrei Spanoche - Santa Clara CA, US
Craig Norman Lambert - San Jose CA, US
Michael W. Caldwell - Santa Clara CA, US
Jingquan Chen - San Jose CA, US

International Classification:

G05F 1/10

US Classification:

327538

Abstract:

The voltage applied to an integrated circuit is controlled by a temporal process monitor formed as part of the integrated circuit. The temporal process monitor includes a voltage controlled oscillator for producing a first output signal having a first period. A comparator compares the first period to one or more reference values. Should the first period be greater than a first selected reference value the comparator sends a signal to increase the voltage being supplied to the integrated circuit. Should the first period be less than a second selected reference value, the comparator sends a signal to decrease the voltage applied to the integrated circuit. In some embodiments a scaling circuit is provided for producing a second output signal having a second period different from (typically but not necessarily longer than) the first period. By placing the temporal process monitor on an integrated circuit chip, process variations and environmental factors which affect the performance of the integrated circuit can be automatically compensated so that the integrated circuit performs within specifications. Two or more temporal process monitors can be placed on a single integrated circuit chip or on different integrated circuit chips and the longest period produced by the temporal process monitors can be used to control the voltage supplied to all the sections of the integrated circuit chip associated with the temporal process monitors or to all the integrated circuit chips associated with the temporal process monitors.

US Patent:

20080278223, Nov 13, 2008

Filed:

Feb 2, 2007

Appl. No.:

11/670547

Inventors:

KENT KERNAHAN - CUPERTINO CA, US
MILTON D. RIBEIRO - SUNNYVALE CA, US
CRAIG NORMAN LAMBERT - SUNNYVALE CA, US
SORIN ANDREI SPANOCHE - SUNNYVALE CA, US
JINGQUAN CHEN - SUNNYVALE CA, US
MICHAEL W. CALDWELL - SANTA CLARA CA, US

International Classification:

G05F 1/10
G05F 1/577

US Classification:

327538, 323267

Abstract:

The voltage applied to an integrated circuit is controlled by a temporal process monitor formed as part of the integrated circuit. The temporal process monitor includes a voltage controlled oscillator for producing a first output signal having a first period. A comparator compares the first period to one or more reference values. Should the first period be greater than a first selected reference value the comparator sends a signal to increase the voltage being supplied to the integrated circuit. Should the first period be less than a second selected reference value, the comparator sends a signal to decrease the voltage applied to the integrated circuit. In some embodiments a scaling circuit is provided for producing a second output signal having a second period different from (typically but not necessarily longer than) the first period. By placing the temporal process monitor on an integrated circuit chip, process variations and environmental factors which affect the performance of the integrated circuit can be automatically compensated so that the integrated circuit performs within specifications. Two or more temporal process monitors can be placed on a single integrated circuit chip or on different integrated circuit chips and the longest period produced by the temporal process monitors can be used to control the voltage supplied to all the sections of the integrated circuit chip associated with the temporal process monitors or to all the integrated circuit chips associated with the temporal process monitors. In some embodiments voltages related to the frequency of a temporal process monitor signal and the frequency of a fixed frequency clock are provided to an error amplifier, which changes the voltage applied to the integrated circuit such that the two frequencies are the same.

US Patent:

58050051, Sep 8, 1998

Filed:

Aug 22, 1997

Appl. No.:

8/918703

Inventors:

Jasleen M. Raisinghani - Sunnyvale CA
Craig N. Lambert - San Jose CA

Assignee:

Exar Corporation - Fremont CA

International Classification:

H03K 19094

US Classification:

327333

Abstract:

A voltage level converter circuit is presented that is capable of independently adjusting the falling edge and rising edge delays of the output signal. The circuit includes two separate transconductance amplifiers each biased independently. Each one of the transconductance amplifiers separately drives an output transistor. The circuit is particularly suited for converting ECL signals to CMOS logic levels.

US Patent:

56252811, Apr 29, 1997

Filed:

Jun 16, 1995

Appl. No.:

8/491465

Inventors:

Craig N. Lambert - San Jose CA

Assignee:

Exar Corporation - San Jose CA

International Classification:

G05F 316

US Classification:

323315

Abstract:

A circuit technique for improving power supply rejection of current mirror circuits having multiple outputs. An input reference current is preadjusted for error caused by power supply variations and then mirrored through a cascade of current mirror circuits. In one embodiment an opamp loop forces the output of a current mirror circuit to be substantially equal to the reference current. This current is then used in subsequent mirroring stages to obtain various outputs. The circuit eliminates the need for including an error-subtraction transistor at every output.