Craig L Nelson

US Patent:

59283629, Jul 27, 1999

Filed:

Apr 29, 1997

Appl. No.:

8/841118

Inventors:

Louis A. Cardillo - Palo Alto CA
Sandro H. Pintz - Menlo Park CA
Craig A. Nelson - Aptos CA
Landau F. Edouard - San Jose CA

Assignee:

CagEnt Technologies, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

713200

Abstract:

Authentication mechanism for interactive home entertainment systems using plug-in cards which do contain software as well as cards which do not contain software. A security bit stream is generated by circuitry on the card and checked by the base system while the system is operating, but only a single signal line of the interface is used for the bit stream. The card also includes a ROM which contains data to be downloaded to the base system. The ROM data is downloaded to the base system via the same signal line of the interface as the serial bit stream. The signal line is used for ROM data download while the base system asserts a "reset" signal, and is used to carry the serial bit stream for authentication purposes whenever the reset signal is negated.

US Patent:

58090061, Sep 15, 1998

Filed:

May 31, 1996

Appl. No.:

8/655961

Inventors:

Hedley C. Davis - Fremont CA
Craig A. Nelson - Aptos CA
Glenn J. Keller - Los Gatos CA

Assignee:

Cagent Technologies, Inc. - Redwood City CA

International Classification:

G11B 700

US Classification:

3692754

Abstract:

Copy-protected optical disk format, optical disk recording apparatus for creating disks having such formats and optical disk reading apparatus for reading disks having such formats and for determining whether the disks are authentic. In one aspect, an authentic optical disk has data bit indications along a spiral centerline of the disk, and these data bit indications define a radial wobble which has substantially greater energy at a predefined frequency f. sub. CPW (such as f. sub. CC /392) than at a frequency of f. sub. CC /196, where f. sub. CC is the spatial channel clock frequency. In another aspect, an authorized optical disk has data bit indications along a substantially spiral centerline of the disk, according to a channel clock whose frequency varies across the disk. The disk further has stored thereon an indication of the number of such channel clock cycles which occur along a predetermined test segment of the centerline, optionally together with a pointer to the test segment. Since normal data stream copying techniques do not copy the exact channel clock rates on the disk, and since the copying equipment will inherently introduce its own channel clock variations across the resulting disk, the predetermined test segment on the copy will not have the number of channel clocks as that specified by the data indicating the number of channel clock cycles to expect along the test segment.

US Patent:

51135116, May 12, 1992

Filed:

Jun 2, 1989

Appl. No.:

7/360357

Inventors:

Craig Nelson - Redwood City CA
Javier Solis - Santa Clara CA
David L. Needle - Alameda CA

Assignee:

Atari Corporation - Sunnyvale CA

International Classification:

G06F 1202
G06F 1200

US Classification:

395425

Abstract:

A system (60) for predicting CPU addresses includes a CPU (34) connected by bus (62) to page mode address predicting circuit (64). The page mode address predicting circuit (64) is connected to memory arbitration circuits (66) by bus (68). The memory arbitration circuits (66) are connected to RAM (42) by address, data and control busses (44), (46) and (48). The CPU (34), page mode address predicting circuit (64) and the memory arbitration circuits 66 are contained in a microprocessor integrated circuit (32). The page mode predicting circuit 64 examines signals from the CPU (34) to be supplied to the data bus (46) at the time of a SYNC pulse. This operation results in examination of the first byte of a CPU instruction to determine how many of the following memory accesses will be able to be carried out in high speed mode. If it is determined that the next memory access will be able to be carried out in the high speed mode, then the next memory cycle is performed using a high speed access mode of the RAM (42), e. g. page mode access.