Curtis J Garrett

US Patent:

59593407, Sep 28, 1999

Filed:

Aug 30, 1996

Appl. No.:

8/707815

Inventors:

Chang-Feng Wan - Dallas TX
Richard Scott List - Dallas TX
Curtis Gene Garrett - Garland TX
Dwight U. Bartholomew - Dallas TX

Assignee:

DRS Technologies, Inc. - Parsippany NJ

International Classification:

H01L 3100

US Classification:

257443

Abstract:

This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

US Patent:

61272035, Oct 3, 2000

Filed:

May 5, 1999

Appl. No.:

9/304953

Inventors:

Chang-Feng Wan - Dallas TX
Richard Scott List - Dallas TX
Curtis Gene Garrett - Garland TX
Dwight U. Bartholomew - Dallas TX

Assignee:

DRS Technologies, Inc. - Parsippany NJ

International Classification:

H01L 21324

US Classification:

438 67

Abstract:

This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.