Curtis Matheson Webster

age ~63

from San Ramon, CA

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Curtis Webster Phones & Addresses

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Location:

San Francisco Bay Area

Industry:

Semiconductors

Skills:

Verilog

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Position:

Clerk at Wells Fargo Home Mortgage

Location:

Anchorage, Alaska

Industry:

Banking

Work:

Wells Fargo Home Mortgage since Jun 1989
Clerk

System And Method For Gate Training In A Memory System
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US Patent:

20120307577, Dec 6, 2012
Filed:

May 30, 2011
Appl. No.:

13/118499
Inventors:

SRINIVAS SRIADIBHATLA - Bangalore, IN
Curtis Matheson Webster - San Ramon CA, US
International Classification:

G11C 7/22
US Classification:

365193
Abstract:

A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.

Bit Error Testing And Training In Double Data Rate (Ddr) Memory System
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US Patent:

20140029364, Jan 30, 2014
Filed:

Jul 27, 2012
Appl. No.:

13/559741
Inventors:

Dharmesh N. Bhakta - Dublin CA, US
Derrick Butt - Dublin CA, US
Curtis M. Webster - San Ramon CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G11C 29/00
US Classification:

365201
Abstract:

DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane.