Cynthia Diana Allison

US Patent:

60467525, Apr 4, 2000

Filed:

Feb 9, 1999

Appl. No.:

9/246399

Inventors:

Dale Kirkland - Madison AL
Cynthia E. Allison - Madison AL
James Paul Turner - Huntsville AL
Joseph Clay Terry - Huntsville AL
Jeffrey S. Ford - Madison AL

Assignee:

Intergraph Corporation - Huntsville AL

International Classification:

G06F 1580

US Classification:

345505

Abstract:

A graphics accelerator includes a plurality of digital signal processors that are arranged in a self-regulating, peer-to-peer configuration. Accordingly, the processors cooperate to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. To that end, each processor includes a request bus, an input in communication with the request bus, and an output coupled to a sequencer for ordering graphics requests processed by the digital signal processors.

US Patent:

59175028, Jun 29, 1999

Filed:

Dec 5, 1996

Appl. No.:

8/761104

Inventors:

Dale L. Kirkland - Madison AL
Cynthia E. Allison - Madison AL
James P. Turner - Huntsville AL
Joseph C. Terry - Huntsville AL
Jeffrey S. Ford - Madison AL

Assignee:

Intergraph Corporation - Huntsville AL

International Classification:

G06F 1580

US Classification:

345505

Abstract:

A graphics processing accelerator has a plurality of digital signal processors that each have an output, and an input in communication with a request bus. The digital signal processors are arranged in a peer-to-peer configuration to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. The graphics processing accelerator also may have a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors.

US Patent:

20170148203, May 25, 2017

Filed:

Nov 25, 2015

Appl. No.:

14/952390

Inventors:

- Santa Clara CA, US
Cynthia ALLISON - Madison AL, US
Dale KIRKLAND - Madison AL, US
Jeffrey BOLZ - Cedar Park CA, US
Yury URALSKY - San Jose CA, US
Jonah ALBEN - San Jose CA, US

International Classification:

G06T 15/00
G06T 15/40
G06T 15/50
G06T 17/20
G06T 15/80

Abstract:

A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

US Patent:

20170148204, May 25, 2017

Filed:

Nov 25, 2015

Appl. No.:

14/952400

Inventors:

- Santa Clara CA, US
Cynthia ALLISON - Madison AL, US
Dale KIRKLAND - Madison AL, US
Jeffrey BOLZ - Cedar Park CA, US
Yury URALSKY - San Jose CA, US
Jonah ALBEN - San Jose CA, US

International Classification:

G06T 15/00
G06T 15/40
G06T 15/50
G06T 17/20
G06T 15/80

Abstract:

A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.