Cynthia Satel Allison

US Patent:

20140118381, May 1, 2014

Filed:

Sep 10, 2013

Appl. No.:

14/023309

Inventors:

- Santa Clara CA, US
Robert OHANNESSIAN - Austin TX, US
Cynthia ALLISON - Madison AL, US
Dale L. KIRKLAND - Madison AL, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06T 1/60

US Classification:

345557

Abstract:

One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.