Cynthia Dianne Phillips

US Patent:

7013395, Mar 14, 2006

Filed:

Mar 13, 2001

Appl. No.:

09/805640

Inventors:

Laura Painton Swiler - Albuquerque NM, US
Cynthia A. Phillips - Albuquerque NM, US

Assignee:

Sandra Corporation - Albuquerque NM

International Classification:

H04L 9/00
G06F 11/30

US Classification:

713201, 713151, 713152, 713153, 713188

Abstract:

A computer system analysis tool and method that will allow for qualitative and quantitative assessment of security attributes and vulnerabilities in systems including computer networks. The invention is based on generation of attack graphs wherein each node represents a possible attack state and each edge represents a change in state caused by a single action taken by an attacker or unwitting assistant. Edges are weighted using metrics such as attacker effort, likelihood of attack success, or time to succeed. Generation of an attack graph is accomplished by matching information about attack requirements (specified in “attack templates”) to information about computer system configuration (contained in a configuration file that can be updated to reflect system changes occurring during the course of an attack) and assumed attacker capabilities (reflected in “attacker profiles”). High risk attack paths, which correspond to those considered suited to application of attack countermeasures given limited resources for applying countermeasures, are identified by finding “epsilon optimal paths. ”.

US Patent:

7565657, Jul 21, 2009

Filed:

Apr 19, 2005

Appl. No.:

11/110206

Inventors:

Vitus J. Leung - Albuquerque NM, US
Cynthia A. Phillips - Albuquerque NM, US
Michael A. Bender - East Northport NY, US
David P. Bunde - Urbana IL, US

Assignee:

Sandia Corporation - Albuquerque NM

International Classification:

G06F 15/173

US Classification:

718104, 709238

Abstract:

In a multiple processor computing apparatus, directional routing restrictions and a logical channel construct permit fault tolerant, deadlock-free routing. Processor allocation can be performed by creating a linear ordering of the processors based on routing rules used for routing communications between the processors. The linear ordering can assume a loop configuration, and bin-packing is applied to this loop configuration. The interconnection of the processors can be conceptualized as a generally rectangular 3-dimensional grid, and the MC allocation algorithm is applied with respect to the 3-dimensional grid.

US Patent:

20190079729, Mar 14, 2019

Filed:

Sep 8, 2017

Appl. No.:

15/699077

Inventors:

- Albuquerque NM, US
Ojas D. Parekh - Albuquerque NM, US
Cynthia A. Phillips - Albuquerque NM, US

International Classification:

G06F 7/483
G06F 7/487
G06F 17/16
G06F 17/12

Abstract:

A method of increasing an efficiency at which a plurality of threshold gates arranged as neuromorphic hardware is able to perform a linear algebraic calculation having a dominant size of N. The computer-implemented method includes using the plurality of threshold gates to perform the linear algebraic calculation in a manner that is simultaneously efficient and at a near constant depth. “Efficient” is defined as a calculation algorithm that uses fewer of the plurality of threshold gates than a naïve algorithm. The naïve algorithm is a straightforward algorithm for solving the linear algebraic calculation. “Constant depth” is defined as an algorithm that has an execution time that is independent of a size of an input to the linear algebraic calculation. The near constant depth comprises a computing depth equal to or between O(log(log(N)) and the constant depth.