Dale E Hocevar

US Patent:

6690750, Feb 10, 2004

Filed:

Dec 23, 1999

Appl. No.:

09/471430

Inventors:

Dale E. Hocevar - Plano TX
Alan Gatherer - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03D 100

US Classification:

375341, 375340, 714786, 714795

Abstract:

A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

US Patent:

6901118, May 31, 2005

Filed:

Dec 18, 2000

Appl. No.:

09/739860

Inventors:

Dale E. Hocevar - Plano TX, US
Raphael Defosseux - Cagnes sur Mer, FR
Armelle Laine - Antibes, FR

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03D001/00
H04B001/69
H03M013/03

US Classification:

375341, 375130, 714786

Abstract:

A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory. The path differences associated with the ACS stage and the next ACS stage provide a reliability estimation of the correctness of the path decisions.

US Patent:

6934343, Aug 23, 2005

Filed:

Nov 13, 2001

Appl. No.:

10/007977

Inventors:

Dale E. Hocevar - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03D001/00
H04L027/06

US Classification:

375341, 375262, 714795, 714796

Abstract:

By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can be counted. After decoding this count information, it can be used with the initial and final state metric values from the decoder to compute the desired full path metric. The method only requires monitoring state metric wrap-arounds moving in one direction and hence only needs to increment the extra counter as opposed to having to do likewise in the opposite direction. In another embodiment, the method can handle both forward and backward progressions by incrementing and decrementing a counter.

US Patent:

7139959, Nov 21, 2006

Filed:

Mar 23, 2004

Appl. No.:

10/806879

Inventors:

Dale E. Hocevar - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 13/11

US Classification:

714752

Abstract:

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit () is disclosed. The LDPC code is arranged as a parity check matrix (H) whose rows and columns represent check sums and input nodes, respectively. The parity check matrix is grouped into subsets of check sum rows, in which the column weight is a maximum of one. The decoder circuitry includes a parity check value estimate memory (). Adders () generate extrinsic estimates, from immediately updated input node probability estimates, and the extrinsic estimates are applied to parity check update circuitry () for generating new parity check sum value estimates. These parity check sum value estimates are stored back into the memory (), and after addition with the extrinsic estimates, are stored in a column sum memory () of a corresponding bit update circuit () as updated probability values for the input nodes.

US Patent:

7162684, Jan 9, 2007

Filed:

Nov 28, 2003

Appl. No.:

10/724280

Inventors:

Dale E. Hocevar - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 11/00
H03M 13/00

US Classification:

714800

Abstract:

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which a left-hand portion of the parity check matrix is arranged as an identity macro matrix, each entry of the macro matrix corresponding to a permutation matrix having zero or more circularly shifted diagonals. The encoder circuitry includes a cyclic multiply unit, which includes a circular shift unit for shifting a portion of the information word according to shift values stored in a shift value memory for the matrix entry, and a bitwise exclusive-OR function for combining the shifted entry with accumulated previous values for that matrix entry. Circuitry for solving parity bits for row rank deficient portions of the parity check matrix is also included in the encoder circuitry.

US Patent:

7178080, Feb 13, 2007

Filed:

Dec 26, 2002

Appl. No.:

10/329597

Inventors:

Dale E. Hocevar - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 13/05
H03M 13/03

US Classification:

714752, 714757, 714780

Abstract:

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (H). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes.

US Patent:

7181676, Feb 20, 2007

Filed:

Feb 11, 2005

Appl. No.:

11/056755

Inventors:

Dale E. Hocevar - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 13/45

US Classification:

714780

Abstract:

A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the plurality of elements into probability values by dividing the rows of at least one column of a parity check matrix associated with the codeword into groups and processing at least some of the groups separately.

US Patent:

7506238, Mar 17, 2009

Filed:

Aug 10, 2005

Appl. No.:

11/201391

Inventors:

Dale E. Hocevar - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 13/00

US Classification:

714781, 714758

Abstract:

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.