Dale K Wong

US Patent:

6389579, May 14, 2002

Filed:

Jan 26, 1999

Appl. No.:

09/238648

Inventors:

Christopher E. Phillips - San Jose CA
Dale Wong - San Francisco CA
Laurence H. Cooke - Los Gatos CA

Assignee:

Chameleon Systems - Los Altos CA

International Classification:

G06F 1750

US Classification:

716 6

Abstract:

An integrated circuit which contains a processor, and configurable logic with configuration memory such that the configurable logic can emulate a large memory array when the contents of the array are very sparse. This structure allows for fast access and a continuous updating capability while remaining internal to the chip. A methodology for recompressing the contents of the configurable logic while updating the configurable logic is also described.

US Patent:

6693456, Feb 17, 2004

Filed:

Aug 3, 2001

Appl. No.:

09/923294

Inventors:

Dale Wong - San Francisco CA

Assignee:

Leopard Logic Inc. - Cupertino CA

International Classification:

H03K 19173

US Classification:

326 41, 326 38, 710317

Abstract:

An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.

US Patent:

6708325, Mar 16, 2004

Filed:

May 31, 2000

Appl. No.:

09/446758

Inventors:

Laurence H. Cooke - Los Gatos CA
Christopher E. Phillips - San Jose CA
Dale Wong - San Francisco CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 944

US Classification:

717124, 717140, 716 17

Abstract:

A computer implemented method for automatically compiling a computer program written in a high level programming language into an intermediate data structure. The data structure is analyzed to identify critical blocks of logic, which can be implemented as an application specific integrated circuit (ASIC), to improve overall performance. The critical blocks of logic are transformed into new equivalent logic with maximal data parallelism. The parallelized logic is then translated into a Boolean gate representation, which is suitable for implementation on an ASIC. The ASIC may be coupled with a generic microprocessor via custom instruction for the microprocessor. The original computer program is then compiled into object code with the new expanded target instruction set.

US Patent:

6801052, Oct 5, 2004

Filed:

Oct 11, 2002

Appl. No.:

10/269830

Inventors:

Daniel J. Pugh - San Jose CA
Andrew W. Fox - Pacific Grove CA
Dale Wong - San Francisco CA

Assignee:

Leopard Logic, Inc. - Cupertino CA

International Classification:

H01L 2500

US Classification:

326 39, 326 38, 326 41, 326 46

Abstract:

A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

US Patent:

6888371, May 3, 2005

Filed:

Oct 29, 2002

Appl. No.:

10/283019

Inventors:

Dale Wong - San Francisco CA, US

Assignee:

Leopard Logic, Inc. - Cupertino CA

International Classification:

H03K019/173

US Classification:

326 38, 326 41, 326 47

Abstract:

A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other elements of the integrated circuit. A control portion of the interface provides selection control bits to the interconnect multiplexer to make the desired connection configuration. Programmable latches in the control portion hold the selection bits which are loaded into the latches at the same time configuration bits are loaded into the integrated circuit to program the FPGA core. Alternatively, the control portion can be implemented by another FPGA core which is configured as a state machine to generate the selection control bits.

US Patent:

6940308, Sep 6, 2005

Filed:

Jan 23, 2004

Appl. No.:

10/764216

Inventors:

Dale Wong - San Francisco CA, US

Assignee:

Leopard Logic Inc. - Cupertino CA

International Classification:

H03K019/173
G06F007/38

US Classification:

326 41, 326 38, 710317

Abstract:

An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.

US Patent:

7009421, Mar 7, 2006

Filed:

Sep 27, 2004

Appl. No.:

10/951309

Inventors:

Daniel J. Pugh - San Jose CA, US
Andrew W. Fox - Pacific Grove CA, US
Dale Wong - San Francisco CA, US

Assignee:

Agate Logic, Inc. - Cupertino CA

International Classification:

H03K 19/173
G06F 17/50

US Classification:

326 38, 326 39, 326 40, 716 7, 716 17

Abstract:

A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

US Patent:

7502920, Mar 10, 2009

Filed:

Dec 4, 2003

Appl. No.:

10/728551

Inventors:

Christopher E. Phillips - San Jose CA, US
Dale Wong - San Francisco CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00
G06F 15/177

US Classification:

713100, 713 1, 711 1, 326 37

Abstract:

The present invention, generally speaking, provides a hierarchy of configuration storage. The highest level of the hierarchy is an active configuration store; the lowest level is an off-chip configuration store; in between are one or more levels of configuration stores. Every configuration is promoted from the lowest off-chip level, through each level, up to the highest active level. Each ascending level of the hierarchy has a decreasing latency time required to promote a configuration to the next higher level of the hierarchy, and a decreasing amount of available storage. This separation into levels allows the amount of available storage to be adjusted depending on the inherent latency of the level's storage mechanism, where a longer latency requires a larger cache. This in turn allows the total required storage for a given performance level to be minimized.