Dam Sunwoo

US Patent:

20110307664, Dec 15, 2011

Filed:

Jun 10, 2010

Appl. No.:

12/801484

Inventors:

Nigel Charles Paver - Austin TX, US
Stuart David Biles - Bury St. Edmunds, GB
Dam Sunwoo - Austin TX, US
Prakash Shyamlal Ramrakhyani - Austin TX, US

Assignee:

ARM LIMITED - Cambridge

International Classification:

G06F 12/08
G06F 12/00

US Classification:

711128, 711133, 711E12001, 711E12018, 711E12022

Abstract:

A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilisation, thereby giving rise to both performance improvements and power consumption reductions.

US Patent:

20220357953, Nov 10, 2022

Filed:

May 10, 2021

Appl. No.:

17/315737

Inventors:

- Cambridge, GB
Yasuo ISHII - Austin TX, US
Krishnendra NATHELLA - Austin TX, US
Dam SUNWOO - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

US Patent:

20230029860, Feb 2, 2023

Filed:

Jul 29, 2021

Appl. No.:

17/388927

Inventors:

- Cambridge, GB
Alejandro Rico Carro - Austin TX, US
Dam Sunwoo - Austin TX, US
Saurabh Pijuskumar Sinha - Schertz TX, US
Jamshed Jalal - Austin TX, US

International Classification:

G06F 12/0811
G06F 12/084
G06F 12/0813
H04L 12/933
H04L 12/717

Abstract:

Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

US Patent:

20210373889, Dec 2, 2021

Filed:

May 29, 2020

Appl. No.:

16/887442

Inventors:

- Cambridge, GB
Krishnendra NATHELLA - Austin TX, US
Jaekyu LEE - Austin TX, US
Dam SUNWOO - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38
G06F 9/52
G06F 9/54
G06F 12/0862
G06F 12/1027

Abstract:

An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and pref etch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of pref etch requests in dependence on reception of the trigger.

US Patent:

20210067335, Mar 4, 2021

Filed:

Aug 26, 2019

Appl. No.:

16/550598

Inventors:

- Cambridge, GB
Yasuo ISHII - Austin TX, US
Dam SUNWOO - Austin TX, US

International Classification:

H04L 9/08

Abstract:

A data processing apparatus is provided that includes storage circuitry. Communication circuitry responds to an access request comprising a requested index with an access response comprising requested data. Coding circuitry performs a coding operation using a current key to: translate the requested index to an encoded index of the storage circuitry at which the requested data is stored or to translate encoded data stored at the requested index of the storage circuitry to the requested data. The current key is based on an execution environment. Update circuitry performs an update, in response to the current key being changed, of: the encoded index of the storage circuitry at which the requested data is stored or the encoded data.

US Patent:

20210026826, Jan 28, 2021

Filed:

Jul 23, 2019

Appl. No.:

16/519498

Inventors:

- Cambridge, GB
Dam Sunwoo - Austin TX, US

International Classification:

G06F 16/22

Abstract:

Briefly, example methods, apparatuses, devices, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques to access entries in a hash table. In a particular implementation, a hash operation may be selected from between or among multiple hash operations to map key values to entries in a hash table.

US Patent:

20200364154, Nov 19, 2020

Filed:

May 15, 2019

Appl. No.:

16/412674

Inventors:

- Cambridge, GB
Dam SUNWOO - Austin TX, US

International Classification:

G06F 12/12
G06F 9/38

Abstract:

An apparatus and method are provided for controlling allocation of information into a cache storage. The apparatus has processing circuitry for executing instructions, and for allowing speculative execution of one or more of those instructions. A cache storage is also provided having a plurality of entries to store information for reference by the processing circuitry, and cache control circuitry is used to control the cache storage, the cache control circuitry comprising a speculative allocation tracker having a plurality of tracking entries. The cache control circuitry is responsive to a speculative request associated with the speculative execution, requiring identified information to be allocated into a given entry of the cache storage, to allocate a tracking entry in the speculative allocation tracker for the speculative request before allowing the identified information to be allocated into the given entry of the cache storage. The allocated tracking entry is employed to maintain restore information sufficient to enable the given entry to be restored to an original state that existed prior to the identified information being allocated into the given entry. The cache control circuitry is further responsive to a mis-speculation condition being detected in respect of the speculative request, to employ the restore information maintained in the allocated tracking entry for that speculative request in order to restore the given entry in the cache storage to the original state. Such an approach can provide robust protection against speculation-based cache timing side-channel attacks whilst alleviating the performance and/or power consumption issues associated with known techniques.

US Patent:

20200097409, Mar 26, 2020

Filed:

Sep 24, 2018

Appl. No.:

16/139160

Inventors:

- Cambridge, GB
Chris Abernathy - Austin TX, US
Huzefa Moiz Sanjeliwala - Austin TX, US
Dam Sunwoo - Austin TX, US
Balaji Vijayan - Austin TX, US

International Classification:

G06F 12/0862
G06F 9/30

Abstract:

A variety of data processing apparatuses are provided in which stride determination circuitry determines a stride value as a difference between a current address and a previously received address. Stride storage circuitry stores an association between stride values determined by the stride determination circuitry and a frequency during a training period. Prefetch circuitry causes a further data value to be proactively retrieved from a further address. The further address is the current address modified by a stride value in the stride storage circuitry having a highest frequency during the training period. The variety of data processing apparatuses are directed towards improving efficiency by variously disregarding certain candidate stride values, considering additional further addresses for prefetching by using multiple stride values, using feedback to adjust the training process and compensating for page table boundaries.