Dan Moy

US Patent:

6426252, Jul 30, 2002

Filed:

Oct 25, 1999

Appl. No.:

09/427256

Inventors:

Carl J. Radens - LaGrangeville NY
Gary B. Bronner - Stormville NY
Tze-chiang Chen - Yorktown Heights NY
Bijan Davari - Mahopac NY
Jack A. Mandelman - Stormville NY
Dan Moy - Bethel CT
Devendra K. Sadana - Pleasantville NY
Ghavam Ghavami Shahidi - Yorktown Heights NY
Scott R. Stiffler - Amenia NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218242

US Classification:

438243, 438155, 438248, 438257

Abstract:

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls.

US Patent:

6566177, May 20, 2003

Filed:

Oct 25, 1999

Appl. No.:

09/427257

Inventors:

Carl J. Radens - LaGrangeville NY
Gary B. Bronner - Stormville NY
Tze-chiang Chen - Yorktown Heights NY
Bijan Davari - Mahopac NY
Jack A. Mandelman - Stormville NY
Dan Moy - Bethel CT
Devendra K. Sadana - Pleasantville NY
Ghavam Ghavami Shahidi - Yorktown Heights NY
Scott R. Stiffler - Amenia NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438152, 438388, 438392

Abstract:

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate.

US Patent:

6538299, Mar 25, 2003

Filed:

Oct 3, 2000

Appl. No.:

09/678315

Inventors:

Young H. Kwark - Chappaqua NY
Dan Moy - Bethel CT
Mark B. Ritter - Danbury CT
Dennis L. Rogers - Croton on Hudson NY
Jeffrey J. Welser - Stamford CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31075

US Classification:

257458, 257452, 257465, 257466, 257656

Abstract:

A semiconductor device (and method for forming the device) includes a silicon-on-insulator (SOI) wafer formed on a substrate surface. An isolation trench in the wafer surface surrounds alternating p-type trenches and n-type trenches and electrically isolates the device from the substrate, thereby allowing the device to be effectively utilized as a differential detector in an optoelectronic circuit.

US Patent:

6555891, Apr 29, 2003

Filed:

Oct 17, 2000

Appl. No.:

09/690674

Inventors:

Toshiharu Furukawa - Essex Junction VT
Jack A. Mandelman - Stormville NY
Dan Moy - Bethel CT
Byeongju Park - Wappingers Falls NY
William R. Tonti - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

257505, 257513, 257514, 257515, 257516, 257517, 257520, 257347

Abstract:

A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e. g. , silicon nitride) on a pad oxide (e. g. , silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e. g. , by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

US Patent:

6635543, Oct 21, 2003

Filed:

Dec 31, 2002

Appl. No.:

10/335652

Inventors:

Toshiharu Furukawa - Essex Junction VT
Jack A. Mandelman - Stormville NY
Dan Moy - Bethel CT
Byeongju Park - Wappingers Falls NY
William R. Tonti - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

A01L 21331

US Classification:

438311, 438309, 438318, 438341, 438353, 438360, 438151

Abstract:

A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e. g. , silicon nitride) on a pad oxide (e. g. , silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e. g. , by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

US Patent:

6713791, Mar 30, 2004

Filed:

Jan 26, 2001

Appl. No.:

09/770788

Inventors:

Louis L. Hsu - Fishkill NY
Rajiv V. Joshi - Yorktown Heights NY
Fariborz Assaderaghi - Mahopac NY
Dan Moy - Bethel CT
Werner Rausch - Stormville NY
James Culp - Poughkeepsie NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

H01L 2974

US Classification:

257200, 257133, 257147, 257162

Abstract:

A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.

US Patent:

6784072, Aug 31, 2004

Filed:

Jul 22, 2002

Appl. No.:

10/200822

Inventors:

Stephen Richard Fox - Hopewell Junction NY
Neena Garg - Fishkill NY
Kenneth John Giewont - Hopewell Junction NY
Junedong Lee - Hopewell Junction NY
Siegfried Lutz Maurer - Stormville NY
Dan Moy - Bethel CT
Maurice Heathcote Norcott - San Jose CA
Devendra Kumar Sadana - Pleasantville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

438404, 438407, 438528

Abstract:

A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage V.

US Patent:

7492008, Feb 17, 2009

Filed:

Jul 22, 2004

Appl. No.:

10/896812

Inventors:

Stephen Richard Fox - Hopewell Junction NY, US
Neena Garg - Fishkill NY, US
Kenneth John Giewont - Hopewell Junction NY, US
Junedong Lee - Hopewell Junction NY, US
Siegfried Lutz Maurer - Stormville NY, US
Dan Moy - Bethel CT, US
Maurice Heathcote Norcott - San Jose CA, US
Devendra Kumar Sadana - Pleasantville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

257347, 257353, 257E27112

Abstract:

A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage V.