Dan J Robinson

US Patent:

7856576, Dec 21, 2010

Filed:

Apr 25, 2007

Appl. No.:

11/789683

Inventors:

Carson D. Henrion - Ft. Collins CO, US
Dan Robinson - Richardson TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 42, 711128, 711136

Abstract:

In one embodiment, a controller for an associative memory having n ways contains circuitry for sending a request to search an indexed location in each of the n ways for a tag, wherein the tag and an index that is used to denote the indexed location form a memory address. The controller also contains circuitry, responsive to the request, for sending a set of n validity values, each validity value indicating, for a respective way, whether the indexed location is a valid location or a defective location. Additionally, the controller contains circuitry for receiving a hit signal that indicates whether a match to the tag was found at any of the indexed locations, wherein no hit is ever received for a defective location.

US Patent:

8539164, Sep 17, 2013

Filed:

Oct 2, 2008

Appl. No.:

12/244700

Inventors:

Craig Warner - Addison TX, US
Gary Gostin - Plano TX, US
Dan Robinson - Allen TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/00

US Classification:

711141, 711E12037

Abstract:

An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate.

US Patent:

20080256306, Oct 16, 2008

Filed:

Apr 11, 2007

Appl. No.:

11/733857

Inventors:

Craig Warner - Addison TX, US
Dan Robinson - Allen TX, US
John Wastlick - Allen TX, US
Michael Schroeder - Plano TX, US

International Classification:

G06F 12/16

US Classification:

711152

Abstract:

Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.

US Patent:

20080270708, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/741858

Inventors:

Craig Warner - Richardson TX, US
Bryan Hornung - Richardson TX, US
Chris Michael Brueggen - Richardson TX, US
Ryan L. Akkerman - Richardson TX, US
Michael K. Dugan - Richardson TX, US
Gary Gostin - Richardson TX, US
Harvey Ray - Ft. Collins CO, US
Dan Robinson - Richardson TX, US
Christopher Greer - Richardson TX, US

International Classification:

G06F 12/08

US Classification:

711146, 711E12041

Abstract:

A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.

US Patent:

20110238925, Sep 29, 2011

Filed:

Oct 2, 2008

Appl. No.:

13/122544

Inventors:

Dan Robinson - Allen TX, US

International Classification:

G06F 12/08

US Classification:

711141, 711E12026

Abstract:

In one embodiment, there are described a sectored cache system and method of operation. A cache data block comprises separately updatable cache sectors. A common tag block contains metadata for the cache sectors of the data block and is writable as a whole. A pending allocation table (PAT) contains data representing pending writes to the tag block. When writing changes data to the tag block, the changed data is broadcast to the PAT to update data representing other pending writes to the tag block so that when the other pending writes are written to the tag block changed data from received broadcasts is included.