Dan J Skinner

US Patent:

20100281227, Nov 4, 2010

Filed:

Apr 29, 2009

Appl. No.:

12/432610

Inventors:

Robert Walker - Raleigh NC, US
Dan Skinner - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G06F 12/00
G06F 13/14

US Classification:

711149, 710305, 711E12001

Abstract:

Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.

US Patent:

20110047311, Feb 24, 2011

Filed:

Aug 24, 2009

Appl. No.:

12/546258

Inventors:

Dan Skinner - Boise ID, US
J. Thomas Pawlowski - Boise ID, US

International Classification:

G06F 13/36

US Classification:

710308

Abstract:

Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

US Patent:

20110093662, Apr 21, 2011

Filed:

Oct 21, 2009

Appl. No.:

12/603376

Inventors:

Robert M. Walker - Raleigh NC, US
Dan Skinner - Boise ID, US
Todd A. Merritt - Boise ID, US
J. Thomas Pawlowski - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G06F 12/00

US Classification:

711147, 711E12001

Abstract:

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

US Patent:

20110093665, Apr 21, 2011

Filed:

Oct 21, 2009

Appl. No.:

12/603393

Inventors:

Robert M. Walker - Raleigh NC, US
Dan Skinner - Boise ID, US
J. Thomas Pawlowski - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 12/00

US Classification:

711154, 711E12001

Abstract:

Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.

US Patent:

20120314523, Dec 13, 2012

Filed:

Aug 20, 2012

Appl. No.:

13/589844

Inventors:

Robert Walker - Raleigh NC, US
Dan Skinner - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 8/16

US Classification:

36523003

Abstract:

Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.

US Patent:

20220350760, Nov 3, 2022

Filed:

Jul 14, 2022

Appl. No.:

17/864629

Inventors:

- Boise ID, US
Dan Skinner - Boise ID, US
Todd A. Merritt - Boise ID, US
J. Thomas Pawlowski - Boise ID, US

International Classification:

G06F 13/16
G06F 12/0813
G06F 15/78
G06F 3/06
G06F 9/30
G06F 13/40

Abstract:

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

US Patent:

20170024337, Jan 26, 2017

Filed:

Oct 7, 2016

Appl. No.:

15/288077

Inventors:

- Boise ID, US
Dan Skinner - Boise ID, US
Todd A. Merritt - Boise ID, US
J. Thomas Pawlowski - Boise ID, US

International Classification:

G06F 13/16
G06F 13/40
G06F 9/30
G06F 3/06

Abstract:

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

US Patent:

20140244948, Aug 28, 2014

Filed:

May 5, 2014

Appl. No.:

14/269873

Inventors:

- Boise ID, US
Dan Skinner - Boise ID, US
J. Thomas Pawlowski - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 3/06

US Classification:

711154

Abstract:

Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.