University Of Maryland Community Medical Group 4231 Postal Ct STE 102, Pasadena, MD 21122 4105538260 (phone), 4105538261 (fax)
Education:
Medical School Howard University College of Medicine Graduated: 1996
Procedures:
Tubal Surgery D & C Dilation and Curettage Destruction of Benign/Premalignant Skin Lesions Hysterectomy Myomectomy Vaccine Administration Vaginal Repair
Conditions:
Candidiasis of Vulva and Vagina Diabetes Mellitus Complicating Pregnancy or Birth Genital HPV Pregnancy-Induced Hypertension Spontaneous Abortion
Languages:
English Spanish
Description:
Dr. Lee graduated from the Howard University College of Medicine in 1996. He works in Pasadena, MD and specializes in Obstetrics & Gynecology. Dr. Lee is affiliated with University Of Maryland Baltimore Washington Medical Center.
Franciscan Medical GroupFranciscan Medical Clinic Enumclaw 3021 Griffin Ave, Enumclaw, WA 98022 3608256511 (phone), 3608256536 (fax)
Education:
Medical School University of Minnesota Medical School at Minneapolis Graduated: 1988
Languages:
English Spanish
Description:
Dr. Lee graduated from the University of Minnesota Medical School at Minneapolis in 1988. She works in Enumclaw, WA and specializes in Pediatrics and Adolescent Medicine. Dr. Lee is affiliated with St Elizabeth Hospital, St Francis Hospital and St Joseph Medical Center.
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates.
Non-Volatile Floating Gate Memory Cell With Floating Gates Formed In Cavities, And Array Thereof, And Method Of Formation
Bomy Chen - Cupertino CA Dana Lee - Santa Clara CA Bing Yeh - Los Altos Hills CA
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H01L 29788
US Classification:
257317, 257315, 257316
Abstract:
A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.
Array Of Integrated Circuit Units With Strapping Lines To Prevent Punch Through
Dana Lee - Santa Clara CA Yaw Wen Hu - Cupertino CA
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H01L 29788
US Classification:
257316, 257321, 257773
Abstract:
An array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. A first plurality of row lines electrically connect the second region of cells in the same row. A plurality of column lines electrically connect the first region of cells in the same column. A plurality of strap lines connect certain of the row lines with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another, wherein row lines connected to a first strap line are interleaved with row lines connected to a second strap line.
Semiconductor Memory Array Of Floating Gate Memory Cells With Buried Floating Gate
An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.
Non-Volatile Floating Gate Memory Cell With Floating Gates Formed In Cavities, And Array Thereof, And Method Of Formation
Bomy Chen - Cupertino CA, US Dana Lee - Santa Clara CA, US Bing Yeh - Los Altos Hills CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H01L021/336
US Classification:
438257
Abstract:
A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.
Multi-Bit Rom Cell, For Storing On Of N>4 Possible States And Having Bi-Directional Read, An Array Of Such Cells
Bomy Chen - Cupertino CA, US Kai Man Yue - Yuen Long, HK Dana Lee - Santa Clara CA, US Feng Gao - Sunnyvale CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C017/00
US Classification:
365104, 365 94
Abstract:
A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together.
Bi-Directional Read/Program Non-Volatile Floating Gate Memory Cell And Array Thereof, And Method Of Formation
A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.
Sohrab Kianian - Los Altos Hills CA, US Dana Lee - Santa Clara CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H01L029/76
US Classification:
257330, 257329, 438270
Abstract:
Vertical NROM devices are made in a substantially single crystalline silicon substrate having a planar surface. The vertical NROM cell and device has a first region and a second region spaced apart from one another by a channel. A dielectric is spaced apart from the channel to capture charges injected from the channel onto the dielectric. A gate is positioned over the dielectric and spaced apart therefrom and controls the flow of current through the channel. In the improvement of the present invention, a portion of the channel is substantially perpendicular to the top planar surface of the substrate. Methods for making the vertical NROM cell and array are also disclosed.
Name / Title
Company / Classification
Phones & Addresses
Dana N. Lee President
LUCKY'S DOGGY HEAVEN, INC Business Services at Non-Commercial Site
1747 Cherry Ave, San Jose, CA 95125
Dana Lee Managing
Dana Lee LLC Ret Gifts/Novelties
5 Crosby St, New York, NY 10013
Dana R. Lee
DANA R. LEE ENTERPRISES, LC
Dana Lee Manager
Universal Dental Studio Dental Laboratory
1754 Hamilton Ave, San Jose, CA 95125 4084450888
Dana N. Lee President, Manager
UNIVERSAL DENTAL STUDIO, INC Dental Laboratory
PO Box 4082, San Jose, CA 95150 1754 Hamilton Ave, San Jose, CA 95125 4084450888
TALBOTS Peachtree City, GA Nov 2007 to Mar 2012 Assistant Store ManagerTalbots Peachtree City, GA Nov 2007 to Mar 2012 Assistant Store ManagerETHAN ALLEN INTERIORS Peachtree City, GA Aug 2006 to Nov 2007 Design ConsultantEthan Allen Interiors Peachtree City, GA Aug 2006 to Nov 2007 Design Consultant/SalesWILSON & ASSOCIATES ARCHITECTS Atlanta, GA May 2005 to Aug 2006 Project Manager/DesignerWilson & Associates Architects Atlanta, GA May 2005 to Aug 2006 Project Manager/DesignerMUNRO DESIGN Atlanta, GA Sep 2003 to Apr 2005 Designer/FF&E Specialty
Education:
Island Drafting & Technical Institute Amityville, NY 1995 to 1996 Certification in Computer Aided Architectural DraftingHOFSTRA UNIVERSITY Uniondale, NY Theatre Arts & Business
Skills:
Sales, Design, Coaching, Recruiting, Customer Service, MS Office and general computer literacy.
Harrison and Star - Digital and Art Intern (2011) LLNS - Creative Intern (2010-2010) LyonHeart (now LLNS) - Creative Intern (2009-2009) Zooppa - Creative Intern/Campaign Manager (2011-2011)
Education:
University of Washington - Visual Communication Design
Dana “The Ghetto Bohemian...
Work:
The Ghetto Bohemian - Astrologer (2012)
Education:
Western Senior High School
About:
Baltimore born and raised. Student and sharer of astrological insights. Outspoken but diplomatic. Unique, quirky and peculiar. Lover of music, knowledge and a good laugh
Tagline:
The stars in the sky shine a bit brighter when we view them from within
Bragging Rights:
High school grad, loving mom, Army vet, I kick ass
Dana Lee
Work:
Ryerson University - Professor (2004)
Education:
York University - Education, Ryerson University - Radio TV Arts
About:
This is my Google+ Account for the The Care and Feeding of Happiness Novel project. Find out more at www.careandfeedingofhappiness.... !
Tagline:
Professor, Ryerson University
Dana Lee
Work:
Reading Area Community College - Math Instructor (7)
Education:
University of South Carolina - Master of Teaching, University of South Carolina - B.S. in Mathematics
Dana Lee
Work:
Ryerson University - Professor (2004)
Education:
Ryerson University - Radio TV Arts, York University - Education
About:
This is my personal Google+ Account. (Not to be confused with my other one, specifically online for the Care and Feeding of Happiness Novel Project...)
Robertson Elementary School Murray KY 1979-1982, Carter Elementary School Murray KY 1982-1983, Saint Mary School Paducah KY 1984-1985, Jacksonville Beach Sixth Grade Center Jacksonville Beach FL 1985-1986
Community:
Karen Paul, Joyce Reeves
Biography:
Life
I am a work at home mom with my own online business and have 3 children - twin...