Dana L Lee

US Patent:

6593177, Jul 15, 2003

Filed:

Oct 5, 2001

Appl. No.:

09/972179

Inventors:

Dana Lee - Santa Clara CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 2964

US Classification:

438201, 438211, 438257, 438694

Abstract:

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates.

US Patent:

6806531, Oct 19, 2004

Filed:

Apr 7, 2003

Appl. No.:

10/409248

Inventors:

Bomy Chen - Cupertino CA
Dana Lee - Santa Clara CA
Bing Yeh - Los Altos Hills CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257317, 257315, 257316

Abstract:

A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.

US Patent:

6822287, Nov 23, 2004

Filed:

May 30, 2003

Appl. No.:

10/452027

Inventors:

Dana Lee - Santa Clara CA
Yaw Wen Hu - Cupertino CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257316, 257321, 257773

Abstract:

An array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. A first plurality of row lines electrically connect the second region of cells in the same row. A plurality of column lines electrically connect the first region of cells in the same column. A plurality of strap lines connect certain of the row lines with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another, wherein row lines connected to a first strap line are interleaved with row lines connected to a second strap line.

US Patent:

6906379, Jun 14, 2005

Filed:

Aug 28, 2003

Appl. No.:

10/653015

Inventors:

Bomy Chen - Cupertino CA, US
Dana Lee - Santa Clara CA, US
Hieu Van Tran - San Jose CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L029/788
H01L021/8238

US Classification:

257315, 257314, 257316, 257317, 257318, 438201, 438211, 438257

Abstract:

An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

US Patent:

6913975, Jul 5, 2005

Filed:

Jul 6, 2004

Appl. No.:

10/885923

Inventors:

Bomy Chen - Cupertino CA, US
Dana Lee - Santa Clara CA, US
Bing Yeh - Los Altos Hills CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L021/336

US Classification:

438257

Abstract:

A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.

US Patent:

6927993, Aug 9, 2005

Filed:

Aug 14, 2003

Appl. No.:

10/642079

Inventors:

Bomy Chen - Cupertino CA, US
Kai Man Yue - Yuen Long, HK
Dana Lee - Santa Clara CA, US
Feng Gao - Sunnyvale CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C017/00

US Classification:

365104, 365 94

Abstract:

A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together.

US Patent:

6936883, Aug 30, 2005

Filed:

Apr 7, 2003

Appl. No.:

10/409333

Inventors:

Bomy Chen - Cupertino CA, US
Jack Frayer - Boulder Creek CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L029/788

US Classification:

257315, 257239, 257261, 257316, 257324, 257326, 438201, 438211, 438257, 438266, 438591

Abstract:

A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

US Patent:

6940125, Sep 6, 2005

Filed:

Apr 4, 2003

Appl. No.:

10/407627

Inventors:

Sohrab Kianian - Los Altos Hills CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L029/76

US Classification:

257330, 257329, 438270

Abstract:

Vertical NROM devices are made in a substantially single crystalline silicon substrate having a planar surface. The vertical NROM cell and device has a first region and a second region spaced apart from one another by a channel. A dielectric is spaced apart from the channel to capture charges injected from the channel onto the dielectric. A gate is positioned over the dielectric and spaced apart therefrom and controls the flow of current through the channel. In the improvement of the present invention, a portion of the channel is substantially perpendicular to the top planar surface of the substrate. Methods for making the vertical NROM cell and array are also disclosed.