Daniel N Allen

US Patent:

7941592, May 10, 2011

Filed:

Aug 14, 2008

Appl. No.:

12/228795

Inventors:

Randy M. Bonella - Portland OR, US
Daniel J. Allen - Derry NH, US
Thomas J. Holman - Portland OR, US
Chung W. Lam - Hillsborough CA, US
Hiroyuki Sakamoto - Ome, JP

International Classification:

G06F 12/00

US Classification:

711103, 711170, 36518503, 36518518

Abstract:

One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.