Daniel V Bailey

US Patent:

6367025, Apr 2, 2002

Filed:

Feb 1, 1999

Appl. No.:

09/241000

Inventors:

Daniel W. Bailey - Northborough MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 104

US Classification:

713400, 713600

Abstract:

A method and apparatus are provided for improving the data hold timing requirement of the sense amplifier by coupling a pass-gate to its data input ports. Each pass-gate receives a logic level that has developed on an input data signal. When the data is valid, a control signal is asserted that causes the pass-gate to latch the logic level at the input of the sense amplifier. While that logic level is latched, the sense amplifier can generate a corresponding latched output signal and the data signal can transition to a new logic level. Therefore, the pass-gate maintains the logic level at the input of the sense amplifier for the duration of the data hold timing requirement. The pass-gate can be a level-sensitive latch that latches said first logic level in response to the assertion level of the control signal. It includes a first transistor having a drain terminal connected to the data signal, a source terminal connected to the sense amplifier and a gate terminal connected to the control signal. That transistor can be a PMOS or NMOS transistor.

US Patent:

6400186, Jun 4, 2002

Filed:

Apr 21, 1999

Appl. No.:

09/296013

Inventors:

Daniel W. Bailey - Northborough MA
Mark D. Matson - Acton MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G01R 1900

US Classification:

327 55, 327 57, 327198, 365208, 36518911

Abstract:

Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifiers performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

US Patent:

6463547, Oct 8, 2002

Filed:

Dec 8, 1999

Appl. No.:

09/457604

Inventors:

Daniel W. Bailey - Northboro MA
Jeffrey D. Pickholtz - Marlboro MA
Shane L. Bell - Shrewsbury MA
William J. Bowhill - Framingham MA

Assignee:

Compaq Information Technologies Group LP - Houston TX

International Classification:

G06F 104

US Classification:

713500, 713503

Abstract:

A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

US Patent:

6463548, Oct 8, 2002

Filed:

May 10, 1999

Appl. No.:

09/309070

Inventors:

Daniel W. Bailey - Northborough MA
Jeffrey D. Pickholtz - Marlboro MA
Shane L. Bell - Shrewsbury MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 104

US Classification:

713503, 713600

Abstract:

A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.

US Patent:

6473334, Oct 29, 2002

Filed:

Oct 31, 2001

Appl. No.:

10/003335

Inventors:

Daniel William Bailey - Northboro MA
Stephen Felix - Cambridge MA
Stephen E. Liles - Shrewsbury MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G11C 1100

US Classification:

365154

Abstract:

A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell. The write data path couples to the memory cell through an access transistor, and also through a second gate that operates to restrict current leakage from the bit lines. In the preferred embodiment, the second gate comprises a current choke that limits current flow to the memory cell during a read operation.

US Patent:

6480036, Nov 12, 2002

Filed:

Nov 12, 2001

Appl. No.:

09/992850

Inventors:

Daniel W. Bailey - Northborough MA
Mark D. Matson - Acton MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G01R 1900

US Classification:

327 55, 327 57, 327198, 365208, 36518911

Abstract:

A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifiers performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

US Patent:

6529044, Mar 4, 2003

Filed:

Jul 31, 2001

Appl. No.:

09/919294

Inventors:

Daniel William Bailey - Northboro MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

H03K 1900

US Classification:

326 93, 326 95, 326 98, 327211, 327212

Abstract:

A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.

US Patent:

6624663, Sep 23, 2003

Filed:

Oct 31, 2001

Appl. No.:

10/000258

Inventors:

Daniel William Bailey - Northboro MA
Daniel E. Dever - Spencer MA
Ronald P. Preston - Malborough MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H03K 301

US Classification:

326 93, 326 98, 327534

Abstract:

A clock driver is disclosed that minimizes propagation delay, and thus improves the integrity of a clock distribution network. The clock driver preferably is implemented with silicon-on-insulator (SOI) technology, and comprises an inverter with an nFET and pFET that are body-connected. The body connection serves to reduce the body voltage of the pFET, while increasing the body voltage of the nFET. This shifting of the voltage reduces the voltage threshold differential for both the nFET and pFET, which translates into a design that experiences less propagation delay due to voltage variations and fluctuations. If desired, the body voltages may be slightly offset from each other by placing one or more voltage drop transistors in the conductive path between the bodies of the nFET and pFET. In addition, the present invention may be used to design a programmable inverter that can operate in a low power mode, or in a high precision mode.