Daniel A Dean

US Patent:

62562428, Jul 3, 2001

Filed:

May 31, 2000

Appl. No.:

9/583478

Inventors:

Daniel S. Dean - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

365201

Abstract:

A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage V. sub. CC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a V. sub. CC -to-ground voltage drop for the entire refresh interval.