Daniel R Dolan

Address:

10601 Water Lily Ter, Saint Paul, MN 55129

VIN:

1L8MAGJAX7A046808

Make:

Lincoln

Model:

Town Car 4dr Sdn Executi

Year:

2007

US Patent:

7595951, Sep 29, 2009

Filed:

Jun 2, 2006

Appl. No.:

11/445535

Inventors:

Daniel J. Dolan - Cottage Grove MN, US
David W. Kelly - Lino Lakes MN, US
Stephen C. Kuehne - Rosemount MN, US
Nathan M. Rudd - Hastings MN, US
Ross S. Wilson - Menlo Park CA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G11B 15/12

US Classification:

360 62, 360 61

Abstract:

A (e. g. , hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

US Patent:

20050232018, Oct 20, 2005

Filed:

Mar 28, 2005

Appl. No.:

11/091352

Inventors:

Daniel Dolan - Cottage Grove MN, US
James Howley - Broomfield CO, US
Zachary Keirn - Loveland CO, US
German Feyh - Boulder CO, US
Michael Straub - Longmont CO, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G11C016/06

US Classification:

365185220

Abstract:

User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.

US Patent:

20080062551, Mar 13, 2008

Filed:

Sep 13, 2006

Appl. No.:

11/520493

Inventors:

Daniel J. Dolan - Cottage Grove MN, US
Hao Fang - Eden Prairie MN, US
Jeffrey A. Gleason - Burnsville MN, US
Ross S. Wilson - Menlo Park CA, US

International Classification:

G11B 27/36
G11B 5/03

US Classification:

360 31, 360 66

Abstract:

An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.

US Patent:

63178621, Nov 13, 2001

Filed:

Aug 16, 1999

Appl. No.:

9/375828

Inventors:

Daniel J. Dolan - Cottage Grove MN
Scott K. Glenna - Shafer MN
Charles P. Jents - White Bear Township MN

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

G06F 1750
G06F 945
H01L 2500
G11B 502

US Classification:

716 8

Abstract:

A preamplifier chip for a disk drive is modular in layout. Twelve head cells for the preamplifier chip are not lined along the periphery of the chip, but rather are disposed in an array including four rows of three head cells each. The rows are all directed perpendicular to the side with control connection pads. The preferred embodiment allows for a smaller preamplifier chip through increasing the density of head cells on the chip relative to the periphery of the chip usable for head cell connection. The array spaces write portions of the head cells in four spaced lines, minimizing problems associated with heat build up. Spacing between rows of the array can be determined to take maximum advantage of lead pitch on the flex circuit. Modification of the design to a chip for eight or four channels is possible with minimal changes to the design, and minimal reworking of the common circuitry.

US Patent:

20160012846, Jan 14, 2016

Filed:

Jul 11, 2014

Appl. No.:

14/329467

Inventors:

- San Jose CA, US
Daniel J. Dolan - Cottage Grove MN, US
David W. Kelly - Eagan MN, US
Richard Rauschmayer - Longmont CO, US

International Classification:

G11B 20/10
G11B 5/09

Abstract:

A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

US Patent:

20150318014, Nov 5, 2015

Filed:

May 1, 2014

Appl. No.:

14/267354

Inventors:

- San Jose CA, US
David W. Kelly - Eagan MN, US
Daniel J. Dolan - Cottage Grove MN, US
Richard Rauschmayer - Longmont CO, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G11B 20/10

Abstract:

A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

US Patent:

20150318030, Nov 5, 2015

Filed:

May 1, 2014

Appl. No.:

14/267344

Inventors:

- San Jose CA, US
David W. Kelly - Eagan MN, US
Daniel J. Dolan - Cottage Grove MN, US
Richard Rauschmayer - Longmont CO, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G11C 7/10

Abstract:

A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.