Daniel L Edwards

US Patent:

6963728, Nov 8, 2005

Filed:

May 15, 2002

Appl. No.:

10/146214

Inventors:

Daniel R. Edwards - Ypsilanti MI, US
Robert A. DiPaolo - Northville MI, US
Daniel E. Farnstrom - Redford MI, US

Assignee:

Visteon Global Technologies, Inc. - Van Buren Township MI

International Classification:

H04B005/00
H04B001/034

US Classification:

455 412, 455 411, 455 413, 455 95, 455 96, 455 99, 3408547

Abstract:

Cavities within structural members of a motor vehicle or other structure are used for propagation of wireless RF communication signals. The system is particularly adapted for use in structures wherein permanent, fixed transmission guides can be easily provided, and it is especially useful in motor vehicles where it 1) reduces the cost and power requirements of electronic modules using wireless communication, 2) shields the communication channel from outside electromagnetic interference, and 3) allows the propagation of emissions to be substantially restricted to desired regions away from people and electronic devices not in the intended network.

US Patent:

8120273, Feb 21, 2012

Filed:

Oct 28, 2008

Appl. No.:

12/259313

Inventors:

Daniel Robert Edwards - Ypsilanti MI, US

Assignee:

Visteon Global Technologies, Inc. - Van Buren Township MI

International Classification:

H05B 37/02

US Classification:

315291, 315185 R, 315225, 315360

Abstract:

A light control system having a light emitting device to produce a pre-determined light output is disclosed. The light control system includes a power circuit in electrical communication with the light emitting device for transmitting an electrical current to the light emitting device for controlling the light output, a timing circuit in electrical communication with the power circuit, wherein the timing circuit generates a pre-determined timing sequence and regulates a duty cycle of the power circuit in response to the timing sequence, and a feedback circuit in communication with the light emitting devices and the timing circuit, wherein the feedback circuit is adapted to monitor an electrical characteristic of the light emitting devices and control the timing sequence of the timing circuit in response to the electrical characteristics of the light emitting devices.

US Patent:

20120112729, May 10, 2012

Filed:

Nov 8, 2010

Appl. No.:

12/941560

Inventors:

Daniel Robert Edwards - Ypsilanti MI, US
Viren B. Merchant - Canton MI, US
Harold Ryan Macks - Redford MI, US

Assignee:

VISTEON GLOBAL TECHNOLOGIES, INC. - Van Buren Twp. MI

International Classification:

G05F 3/08

US Classification:

323312

Abstract:

A limiter circuit includes a voltage rail having an input and an output, the input receiving an applied input voltage, a switching device in electrical communication with the voltage rail to selective control an electric current flowing through the output of the voltage rail, limiter capacitor in electrical communication with the input of the voltage rail and the switching device, wherein the limiter capacitor and the switching device are in parallel electrical communication between the input and an electrical ground, and a first resistor interposed between the limiter capacitor and the electrical ground, wherein an impedance of the resistor and the limiter capacitor define a time constant for the charging the limiter capacitor, and wherein the time constant of the limiter capacitor controls a voltage applied to the switching device and a current flowing through the output of the voltage rail.

US Patent:

57684464, Jun 16, 1998

Filed:

Sep 29, 1994

Appl. No.:

8/314737

Inventors:

George E. Reasoner - Tecumseh MI
Daniel R. Edwards - Ypsilanti MI
Gerald R. Smith - Farmington MI
Debora Y. Grosse - Ann Arbor MI
Robert C. Kidd - Ann Arbor MI

Assignee:

Unisys Corp. - Blue Bell PA

International Classification:

G06K 954
G06K 960

US Classification:

382304

Abstract:

In a system for processing and imaging documents to develop a stream of digital, video bit sets, each related to a different document is a passing array, this system including an arrangement for simultaneously compressing a number of said bit-sets for different document images and sending the results to output, this arrangement as comprising: a preprocessing stage for distributing each said bit set in a pair, of like parallel bit-compression paths, one, a Master path for half the bits in a set, the other a Slave path for the other half as controlled by The Master, with both input to a common buffer, each compression path being adapted to execute a first compression and then a conditional second compression when certain initial factors are indicated and to provide a real-time-compressed output to this buffer; and both said compressions being performed on a single, two pass stage of a Histogram/Compressor printed circuit board.

US Patent:

57845034, Jul 21, 1998

Filed:

Apr 7, 1995

Appl. No.:

8/418317

Inventors:

John A. Bleecker - Canton MI
George E. Reasoner - Tecumseh MI
Daniel R. Edwards - Ypsilanti MI
Gerald R. Smith - Farmington MI

Assignee:

Unisys Corp - Blue Bell PA

International Classification:

G06K 900

US Classification:

382306

Abstract:

An electronic document-imaging arrangement wherein imaging means generates imaging-bits representing a given document and transfers these bits on a "per-document basis" to various successive electronic processing stages and, finally, to a data base storage unit (DBS); this arrangement also including a tag stage for creating tag bits unique for each such imaged document; these tag bits to be transferred with the imaging bits for each document to each such processing stage that handles the imaging bits, on a per document basis, and finally to DBS interface means for final matching and removal of the tag bits.

US Patent:

56824440, Oct 28, 1997

Filed:

Jun 6, 1996

Appl. No.:

8/660615

Inventors:

George E. Reasoner - Tecumseh MI
Daniel R. Edwards - Ypsilanti MI
Gerald R. Smith - Farmington MI

International Classification:

G06K 900

US Classification:

382306

Abstract:

An electronic document-imaging arrangement which generates imaging-bits representing a given document and transfers these bits on a "per-document basis" to various successive electronic processing stages and, finally, to data base storage; this arrangement also including a tag unit adapted to create "sync-tag" bits unique for each such imaged document and transfer these tag bits, along with the imaging bits, for each document to each processing stage that handles the imaging bits on a per document basis, and finally to an associated interface for final matching and removal of the tag bits.

US Patent:

59996633, Dec 7, 1999

Filed:

Sep 2, 1994

Appl. No.:

8/300666

Inventors:

Daniel R. Edwards - Ypsilanti MI
George R. Reasoner - Tecumseh MI
Gerald R. Smith - Farmington MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06K 936

US Classification:

382298

Abstract:

An arrangement for extracting and processing image data to form an array of re-scaled pixel data, this arrangement being part of a Normalizer/Scaler stage in an image lift/processing system, and including: a scaler for storing N different selectible scaling algorithms; a scaler-output; an input for receiving scanned lines of pixel data and feeding it sequentially line-by-line, pixel-by-pixel to the scaler, the input including "scale factors" for selecting an algorithm; while the scaler includes a mapping stage for executing a two-dimensional mapping of adjacent pixel values and adjacent scanline values; this arrangement also including a command store for storing scaling algorithms, with a command register input for the scale factors. Preferably the scaler also includes a First ROM for storing pixel values at prescribed addresses; a Second ROM for similarly storing previous pixel values, being input in parallel with the First ROM; a Latch to which the ROMs are output; and a pixel Counter reset with each new scan line; with a "current pixel" value input to a prescribed address in the First ROM, along with a "pixel count" number from the Counter, plus an associated scale factor; with an Adder interposed between the ROMs and the Latch to execute addition mapping.

US Patent:

55287050, Jun 18, 1996

Filed:

Aug 26, 1994

Appl. No.:

8/296578

Inventors:

George E. Reasoner - Tecumseh MI
Daniel R. Edwards - Ypsilanti MI
Gerald R. Smith - Farmington MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06K 900

US Classification:

382306

Abstract:

An electronic document-imaging arrangement which generates imaging-bits representing a given document and transfers these bits on a "per-document basis" to various successive electronic processing stages and, finally, to a data base storage; this arrangement also including a tag unit adapted to create "sync-tag" bits unique for each such imaged document and transfer these tag bits, along with the imaging bits, for each document to each processing stage that handles the imaging bits on a per document basis, and finally to an associated interface for final matching and removal of the tag bits.