Daniel E Hopper

US Patent:

7237095, Jun 26, 2007

Filed:

Aug 4, 2005

Appl. No.:

11/197705

Inventors:

Daniel B. Hopper - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9/30
G06F 9/40
G06F 12/00
G06F 1/32

US Classification:

712215, 712205, 712206, 712214, 712217

Abstract:

A method and mechanism for managing shifts in a shifting queue. A reservation station in a processing device includes a queue of shifting entries. On a given cycle, zero, one, or two instructions may be dispatched and stored in the queue. Depending upon the dispatch conditions and the state of the queue, existing entries within the queue may be shifted to make room for the newly dispatched instruction(s) at the top of the queue. Shift vectors are generated which identify entries of the queue which are to be shifted and by how much. A queue management approach is adopted in which three rules are generally followed: (i) Only shift entries that must shift due to dispatch pressure from above; (ii) If an entry must be shifted elsewhere, shift it as far down the array as the particular implementation allows; and (iii) Don't allow the previous conditions to force additional entries to shift that are not required to shift by dispatch pressure.

US Patent:

20110055523, Mar 3, 2011

Filed:

Aug 31, 2009

Appl. No.:

12/551240

Inventors:

David A. Kaplan - Austin TX, US
Daniel B. Hopper - Austin TX, US
Benjamin C. Serebrin - Sunnyvale CA, US

International Classification:

G06F 9/312
G06F 9/22

US Classification:

712214, 712245, 712E09005, 712E09033

Abstract:

A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to the first command issuing, within the computer processor, wherein execution of the second command by the computer processor includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, the method includes a third command issuing within the computer processor, wherein execution of the third command by the computer processor includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

US Patent:

20120124586, May 17, 2012

Filed:

Nov 16, 2010

Appl. No.:

12/947715

Inventors:

Daniel Hopper - Austin TX, US
Suzanne Plummer - Austin TX, US
Christopher D. Bryant - Austin TX, US

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the apparatus. One embodiment of the method includes determining whether a first group, comprising at least one or more instructions, is to be selected from a scheduling queue of a processor for execution using either a first execution mode or a second execution mode. The method also includes, responsive to determining that the first group is to be selected for execution using the second execution mode, preventing selection of the first group until a second group, comprising at least one or more instructions, that entered the scheduling queue prior to the first group is selected for execution.

US Patent:

20150121010, Apr 30, 2015

Filed:

Oct 30, 2013

Appl. No.:

14/067564

Inventors:

- Sunnyvale CA, US
Daniel Hopper - Austin TX, US
John M. King - Austin TX, US
Jeff Rupley - Round Rock TX, US

International Classification:

G06F 9/30
G06F 12/08

US Classification:

711125

Abstract:

Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

US Patent:

20140310506, Oct 16, 2014

Filed:

Apr 11, 2013

Appl. No.:

13/861083

Inventors:

- Sunnyvale CA, US
Daniel Hopper - Austin TX, US
Tarun Nakra - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9/30

US Classification:

712214

Abstract:

The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction.