Daniel Charles Kerr

US Patent:

7074628, Jul 11, 2006

Filed:

Sep 22, 2004

Appl. No.:

10/947069

Inventors:

Bradley J. Albers - Dallas TX, US
Thomas Craig Esry - Orlando FL, US
Daniel Charles Kerr - Orlando FL, US
Edward Paul Martin, Jr. - Orlando FL, US
Oliver Desmond Patterson - Poughkeepsie NY, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 31/26
H01L 21/66

US Classification:

438 14, 438 38, 438 60

Abstract:

A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

US Patent:

7095094, Aug 22, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/953894

Inventors:

Daniel Charles Kerr - Orlando FL, US
Michael Scott Carroll - Orlando FL, US
Amal Ma Hamad - Frisco TX, US
Thiet The Lai - Orlando FL, US
Roger W. Key - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 27/102

US Classification:

257526, 257499, 257506, 257E27015

Abstract:

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

US Patent:

7111517, Sep 26, 2006

Filed:

Jul 29, 2004

Appl. No.:

10/902332

Inventors:

Daniel Charles Kerr - Orlando FL, US
Alan R. Olds - Clermont FL, US
Bradley Curtis Deselms - Longwood FL, US
Dennis P. Biondi - Cocoa FL, US
William A. Russell - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

B08B 3/12

US Classification:

73648, 134 57 R, 134113, 134184, 134902

Abstract:

Apparatus and method are provided for in-situ measurement of vibrational energy applied to a wafer in a process bath of a vibrational cleaning system. The apparatus may be made up of a test wafer comprising an array of pressure sensing elements disposed thereon for monitoring power level variation of a time-varying pressure wave. The time-varying pressure wave is indicative of vibrational energy that would be applied to a wafer in the process bath in the position of the test wafer.

US Patent:

7176781, Feb 13, 2007

Filed:

Sep 29, 2004

Appl. No.:

10/953478

Inventors:

Daniel Charles Kerr - Orlando FL, US
Roger W. Key - Orlando FL, US
Bradley J. Albers - Dallas TX, US
William A. Russell - Orlando FL, US
Alan Sangone Chen - Windermere FL, US

Assignee:

Agere Systems Inc - Allentown PA

International Classification:

H01C 1/012

US Classification:

338309, 338202, 338322

Abstract:

A resistor formed on a material layer of a semiconductor integrated circuit and a method for forming the resistor. The resistor comprises a region of resistive material with a plurality of conductive contacts or plugs in electrical contact with and extending away from the resistive material. A first and a second interconnect line are formed overlying the plugs and in conductive contact with one or more of the plurality of plugs, such that a portion of the resistive material between the first and the second interconnect lines provides a desired resistance. According to a method of the present invention, the plurality of conductive contacts are formed using a first photolithographic mask and the first and the second interconnect lines are formed using a second photolithographic mask. The desired resistance is changed by modifying the first or the second mask such that one or more dimensions of a region of the resistive material between the first and the second interconnect lines is altered.

US Patent:

7253012, Aug 7, 2007

Filed:

Sep 14, 2004

Appl. No.:

10/941665

Inventors:

Daniel Charles Kerr - Orlando FL, US
Roscoe T. Luce - Kissimmee FL, US
Michele Marie Jamison - Sanford FL, US
Alan Sangone Chen - Windermere FL, US
William A. Russell - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 21/00

US Classification:

438 22, 438160, 438942, 438947, 438950, 257E2124, 257E21259

Abstract:

A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. A plurality of guard rings may be used that enclose respective arrays of matched devices arranged over the surface of a semiconductor wafer. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, local and global matching are achieved.

US Patent:

7345364, Mar 18, 2008

Filed:

Sep 30, 2004

Appl. No.:

10/955238

Inventors:

Daniel Charles Kerr - Orlando FL, US
Alan Sangone Chen - Windermere FL, US
Edward Paul Martin, Jr. - Orlando FL, US
Amal Ma Hamad - Frisco TX, US
William A. Russell - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 23/10
H01L 23/34

US Classification:

257707, 257706, 257713, 257E23087, 257E23102, 257E23108, 257E23109

Abstract:

A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.

US Patent:

7407824, Aug 5, 2008

Filed:

May 15, 2007

Appl. No.:

11/748569

Inventors:

Daniel Charles Kerr - Orlando FL, US
Roscoe T. Luce - Kissimmee FL, US
Michele Marie Jamison - Sanford FL, US
Alan Sangone Chen - Windermere FL, US
William A. Russell - Orlando FL, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 21/00

US Classification:

438 22, 438160, 438942, 438947, 438950, 257E2124, 257E21259

Abstract:

A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.

US Patent:

7449388, Nov 11, 2008

Filed:

Jul 18, 2006

Appl. No.:

11/458270

Inventors:

Daniel Charles Kerr - Orlando FL, US
Michael Scott Carroll - Orlando FL, US
Amal Ma Hamad - Frisco TX, US
Thiet The Lai - Orlando FL, US
Roger W. Key - Orlando FL, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/331

US Classification:

438309

Abstract:

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.