Daniel F Mccarthy

US Patent:

55308040, Jun 25, 1996

Filed:

May 16, 1994

Appl. No.:

8/242767

Inventors:

Gregory C. Edgington - Scottsdale AZ
Joseph C. Circello - Phoenix AZ
Daniel M. McCarthy - Phoenix AZ
Richard Duerden - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1126

US Classification:

39518306

Abstract:

A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the "suspended" normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc.