Daniel Gerald Miner

Address:

1427 Dapplegrey Ln, Austin, TX 78727

VIN:

4T4BF3EK4BR169115

Make:

Toyota

Model:

Camry

Year:

2011

US Patent:

6370661, Apr 9, 2002

Filed:

Apr 26, 1999

Appl. No.:

09/299673

Inventors:

Daniel G. Miner - Austin TX

Assignee:

IP-First, LLC - Fremont CA

International Classification:

G11C 2900

US Classification:

714718, 714 31

Abstract:

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

US Patent:

6493839, Dec 10, 2002

Filed:

Oct 3, 2001

Appl. No.:

09/970280

Inventors:

Daniel G. Miner - Austin TX

Assignee:

IP First, LLC - Fremont CA

International Classification:

G11C 2900

US Classification:

714718, 714 31

Abstract:

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

US Patent:

6862704, Mar 1, 2005

Filed:

Sep 7, 2002

Appl. No.:

10/236789

Inventors:

Daniel G. Miner - Austin TX, US

Assignee:

IP-First, LLC - Fremont CA

International Classification:

G11C029/00
H02H003/05

US Classification:

714718, 714 31

Abstract:

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

US Patent:

58896791, Mar 30, 1999

Filed:

Jul 15, 1997

Appl. No.:

8/892640

Inventors:

G. Glenn Henry - Austin TX
Arturo Martin-de-Nicolas - Austin TX
Daniel G. Miner - Austin TX

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G06F 1500

US Classification:

364488

Abstract:

An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and logically merges the fuse states with a default configuration for the functional blocks. The result of the merge operation is stored in a feature control register that individually enables/disables the functional blocks. The control unit also receives a write command from an external source that modifies the feature control register, after the device is shipped from the manufacturer. The control unit selectively blocks writes to the feature control register that attempt to enable/disable functional blocks that should not modified.

US Patent:

58354310, Nov 10, 1998

Filed:

Sep 5, 1997

Appl. No.:

8/924302

Inventors:

Daniel G. Miner - Austin TX
Brian Snider - Round Rock TX

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11O 760

US Classification:

365201

Abstract:

A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.