Daniel J Morris

US Patent:

20100080410, Apr 1, 2010

Filed:

Sep 29, 2008

Appl. No.:

12/240641

Inventors:

LISA SEACAT DELUCA - SAN FRANCISCO CA, US
TRAVIS M. GRIGSBY - AUSTIN TX, US
STEVEN M. MILLER - CARY NC, US
DANIEL D. MORRIS - ROUND ROCK TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06K 9/00
G06F 21/00

US Classification:

382100, 726 2

Abstract:

A photograph processing system that prevents the unpermitted use of photographic media containing a depiction of a protected person, view or item. A permission object is located in physical proximity to the person, view or object being protected. A photograph including the permission object will contain a depiction of the permission object. When the photograph is processed, the photograph processing system scans the photograph for a permission object. If a permission object is found, the system further processes the photograph according to the permission associated with the permission object.

US Patent:

20230075959, Mar 9, 2023

Filed:

May 5, 2022

Appl. No.:

17/737820

Inventors:

- Menlo Park CA, US
Daniel Henry MORRIS - Mountain View CA, US
Edith DALLARD - San Mateo CA, US

International Classification:

G11C 7/10
G11C 7/12
G11C 8/18
G11C 8/08

Abstract:

An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

US Patent:

20230065165, Mar 2, 2023

Filed:

Dec 17, 2021

Appl. No.:

17/554838

Inventors:

- Menlo Park CA, US
Huichu LIU - Santa Clara CA, US
Daniel Henry MORRIS - Mountain View CA, US
Doyun KIM - Seoul, KR

International Classification:

G11C 11/419
G11C 11/418

Abstract:

In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines. The apparatus may comprise a controller configured to: assert a word line associated with a row; perform a sequence of write operations while the word line remains asserted, each write operation corresponding to a bit cell associated with a different column of the plurality of columns and the row, wherein the word line has an elevated voltage relative to a non-elevated voltage during at least a portion of the sequence of write operations; and de-assert the word line after the sequence of write operations are performed.

US Patent:

20230065591, Mar 2, 2023

Filed:

Apr 11, 2022

Appl. No.:

17/658740

Inventors:

- Menlo Park CA, US
Edith DALLARD - San Mateo CA, US
Daniel Henry MORRIS - Mountain View CA, US

International Classification:

G11C 29/44
G11C 29/18
G11C 29/12
G11C 29/00
H03K 19/173
H03K 19/21

Abstract:

In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

US Patent:

20200194663, Jun 18, 2020

Filed:

Dec 12, 2018

Appl. No.:

16/217807

Inventors:

Huichu Liu - Santa Clara CA, US
Daniel Morris - Hillsboro OR, US
Tanay Karnik - Portland OR, US
Sasikanth Manipatruni - Hillsboro OR, US
Kaushik Vaidyanathan - Santa Clara CA, US
Ian Young - Portland OR, US

International Classification:

H01L 43/02
H01L 43/10
H01L 27/22
H03K 19/18

Abstract:

Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

US Patent:

20200091407, Mar 19, 2020

Filed:

Sep 13, 2018

Appl. No.:

16/130905

Inventors:

Huichu LIU - Santa Clara CA, US
Tanay KARNIK - Portland OR, US
Sasikanth MANIPATRUNI - Portland OR, US
Daniel MORRIS - Hillsboro OR, US
Kaushik VAIDYANATHAN - Santa Clara CA, US
Ian YOUNG - Portland OR, US

International Classification:

H01L 43/02
H01L 43/10
G11C 11/16
G11C 11/18
H01L 43/06

Abstract:

An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.

US Patent:

20200091414, Mar 19, 2020

Filed:

Sep 13, 2018

Appl. No.:

16/130912

Inventors:

Huichu Liu - Santa Clara CA, US
Sasikanth Manipatruni - Portland OR, US
Daniel Morris - Hillsboro OR, US
Kaushik Vaidyanathan - Santa Clara CA, US
Tanay Karnik - Portland OR, US
Ian Young - Portland OR, US

International Classification:

H01L 43/04
H01L 43/06
H01L 43/10
G11C 11/16
G11C 11/18

Abstract:

An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

US Patent:

20190043549, Feb 7, 2019

Filed:

Sep 27, 2018

Appl. No.:

16/144896

Inventors:

- Santa Clara CA, US
Daniel H. Morris - San Francisco CA, US
Huichu Liu - Santa Clara CA, US
Dileep J. Kurian - Bangalore, IN
Uygar E. Avci - Portland OR, US
Tanay Karnik - Portland OR, US
Ian A. Young - Portland OR, US

International Classification:

G11C 11/22
G11C 11/413
G06F 1/32

Abstract:

Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.