Daniel J Nelson

US Patent:

6712361, Mar 30, 2004

Filed:

Jul 9, 2002

Appl. No.:

10/192251

Inventors:

Daniel W. Nelson - Rochester MN 55902

Assignee:

Daniel W. Nelson - Rochester MN

International Classification:

A63B 7100

US Classification:

273441, 273153, 273153 S, 463 9, 463 15

Abstract:

A mentally challenging game with computer and physical embodiments in which the goal is to move a primary object from its initial location through a system of platforms and levers to a particular destination. Horizontally movable counterweights also traverse this system, serving to raise and lower lever platforms in such a way as to raise and lower the primary object to its destination.

US Patent:

7443744, Oct 28, 2008

Filed:

Nov 14, 2006

Appl. No.:

11/559431

Inventors:

Derick Gardner Behrends - Rochester MN, US
Peter Thomas Freiburger - Rochester MN, US
Ryan Charles Kivimagi - Chatfield MN, US
Daniel Mark Nelson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/00

US Classification:

365200, 365 63, 36523002

Abstract:

A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

US Patent:

7502276, Mar 10, 2009

Filed:

May 16, 2008

Appl. No.:

12/122185

Inventors:

Derick G. Behrends - Rochester MN, US
Todd A. Christensen - Rochester MN, US
Travis R. Hebig - Rochester MN, US
Daniel M. Nelson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 8/12
G11C 11/413
G11C 8/10
G11C 29/18
G11C 29/26

US Classification:

36523002, 36523003, 36523006, 365201, 365154

Abstract:

A domino read SRAM capable of writing multiple wordlines simultaneously. A read/write multiplexer may allow conventional, single-wordline selection during a read operation, while allowing external logic, such as an ABIST controller, to enable multiple wordlines during a write operation.

US Patent:

7505340, Mar 17, 2009

Filed:

Aug 28, 2007

Appl. No.:

11/845866

Inventors:

Chad Allen Adams - Byron MN, US
Derick Gardner Behrends - Rochester MN, US
Travis Reynold Hebig - Rochester MN, US
Daniel Mark Nelson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/00

US Classification:

365201, 36518908, 36518909

Abstract:

A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

US Patent:

7535776, May 19, 2009

Filed:

Jul 10, 2008

Appl. No.:

12/170993

Inventors:

Derick G. Behrends - Rochester MN, US
Travis R. Hebig - Rochester MN, US
Daniel M. Nelson - Rochester MN, US
Jesse D. Smith - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/41
G11C 11/413
G11C 7/22
G11C 7/10

US Classification:

36518915, 36518905, 36518917, 3651892, 365154, 36523317

Abstract:

A method for passing data from an input to an output of a domino read access path in domino read SRAM memory including receiving at least a portion of the input data from a latch configuration, gating a global precharge signal, gating a bit select circuitry signal, driving the input data statically through a transmission gate of a static bypass multiplexer to the global dot of the domino read SRAM memory, initiating a write around cycle signal, offsetting the write around signal input into the static bypass multiplexer and the precharge signal by at least one phase using a wave shaper, driving the input data from the global dot through a keeper circuit, and driving the input data from the keeper circuit to at least one NAND gate of a pair of cross-coupled NAND gates, the pair of cross-coupled NAND gates being configured in a transparent state.

US Patent:

7714630, May 11, 2010

Filed:

Jun 13, 2008

Appl. No.:

12/138564

Inventors:

Derick G. Behrends - Rochester MN, US
Todd A. Christensen - Rochester MN, US
Travis R. Hebig - Rochester MN, US
Daniel M. Nelson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03H 11/26

US Classification:

327278, 327261, 327263, 327291

Abstract:

The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e. g. 0) or high voltage (e. g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.

US Patent:

7724585, May 25, 2010

Filed:

Aug 20, 2008

Appl. No.:

12/195117

Inventors:

Derick Gardner Behrends - Rochester MN, US
Travis Reynold Hebig - Rochester MN, US
Daniel Mark Nelson - Rochester MN, US
Jesse Daniel Smith - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/06
G06F 17/50

US Classification:

36518914, 36518915, 36518916, 36518906, 365190, 365203, 365156, 716 12, 716 17

Abstract:

A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.

US Patent:

7724586, May 25, 2010

Filed:

Aug 20, 2008

Appl. No.:

12/195151

Inventors:

Chad Allen Adams - Rochester MN, US
Todd Alan Christensen - Rochester MN, US
Peter Thomas Freiburger - Rochester MN, US
Daniel Mark Nelson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/06
G06F 17/50

US Classification:

36518914, 36518915, 36518916, 365190, 365203, 36518906, 365156, 716 12, 716 17

Abstract:

A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.