Daniel G Rice

US Patent:

6988181, Jan 17, 2006

Filed:

Mar 8, 2001

Appl. No.:

09/802289

Inventors:

Ashley Saulsbury - Los Gatos CA, US
Michael Parkin - Palo Alto CA, US
Daniel S. Rice - Oakland CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 15/80

US Classification:

712 24, 712 22

Abstract:

According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.

US Patent:

7020763, Mar 28, 2006

Filed:

Mar 8, 2001

Appl. No.:

09/802108

Inventors:

Ashley Saulsbury - Los Gatos CA, US
Michael Parkin - Palo Alto CA, US
Daniel S. Rice - Oakland CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 15/76

US Classification:

712 24

Abstract:

A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R×N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R×S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2. In accordance with yet another embodiment of the invention, a single VLIW processing instruction comprises R×N-number of P-bit sub-instructions appended together.

US Patent:

7106326, Sep 12, 2006

Filed:

Mar 3, 2003

Appl. No.:

10/378279

Inventors:

Michael F. Deering - Los Altos CA, US
Michael G. Lavelle - Saratoga CA, US
Douglas C. Twilleager - Oakland CA, US
Daniel S. Rice - Oakland CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06T 15/50
G06T 15/60

US Classification:

345426

Abstract:

A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates Cof a point P with respect to a first space to the shadow processing unit. In response to receiving the coordinates C, the shadow processing unit is configured to: (a) transform the coordinate Cto determine map coordinates s and t and a depth value Dfor the point P, (b) access a neighborhood of depth values from a memory using the map coordinates s and t, (c) compare the depth value Dto the depth values of the neighborhood, (d) filter binary results of the comparisons to determine a shadow fraction, and (e) transfer the shadow fraction to the computational unit through the communication bus.

US Patent:

7124160, Oct 17, 2006

Filed:

Mar 8, 2001

Appl. No.:

09/801564

Inventors:

Ashley Saulsbury - Los Altos CA, US
Daniel S. Rice - Oakland CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 7/38

US Classification:

708490

Abstract:

According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operands and the second number of operands. The first source register includes a plurality of first operands and the destination register includes a plurality of results. The number of arithmetic processors are respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.

US Patent:

7558816, Jul 7, 2009

Filed:

Nov 21, 2001

Appl. No.:

09/992064

Inventors:

Ashley Saulsbury - Los Altos CA, US
Daniel S. Rice - Oakland CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 7/38

US Classification:

708445

Abstract:

According to the invention, a process for averaging two pixel values is disclosed. In one step, an instruction is decoded. A plurality of first operands is loaded from a first input register. A plurality of second operands is loaded from a second input register. An average of one of the plurality of first operands and one of the plurality of second operands is produced. The average is stored in an output register.

US Patent:

8280456, Oct 2, 2012

Filed:

Aug 14, 2009

Appl. No.:

12/541415

Inventors:

Dianne K. Hackborn - Santa Clara CA, US
Daniel S. Rice - Decatur GA, US
Amith Yamasani - San Jose CA, US
Jason B. Parks - Santa Clara CA, US
Evan Millar - Pleasanton CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

H04B 17/00
H04M 3/00
H04N 17/02

US Classification:

455574, 455419, 348189, 713340

Abstract:

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a user with feedback regarding power consumption in a battery-operated electronic device. In one aspect, a method performed by data processing apparatus includes identifying, using the data processing apparatus, usage of a hardware component of a battery-operated electronic device that includes the data processing apparatus, attributing the usage of the hardware component to the hardware component or to a software application that uses the hardware component, recording, using the data processing apparatus, a power consumption resulting from the usage, and presenting power consumption feedback to a user using the data processing apparatus. The power consumption feedback identifies the hardware component or the software application of the electronic device and the power consumption resulting from the usage.

US Patent:

8285340, Oct 9, 2012

Filed:

Sep 26, 2011

Appl. No.:

13/245476

Inventors:

Dianne K. Hackborn - Santa Clara CA, US
Daniel S. Rice - Decatur GA, US
Amith Yamasani - San Jose CA, US
Jason B. Parks - Santa Clara CA, US
Evan Millar - Pleasanton CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 1/00
G06F 1/32
H04B 7/10

US Classification:

455567, 455419, 375347, 348189, 702 63, 713300, 713321

Abstract:

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a user with feedback regarding power consumption in a battery-operated electronic device. In one aspect, a method performed by data processing apparatus includes identifying, using the data processing apparatus, usage of a hardware component of a battery-operated electronic device that includes the data processing apparatus, attributing the usage of the hardware component to the hardware component or to a software application that uses the hardware component, recording, using the data processing apparatus, a power consumption resulting from the usage, and presenting power consumption feedback to a user using the data processing apparatus. The power consumption feedback identifies the hardware component or the software application of the electronic device and the power consumption resulting from the usage.

US Patent:

8343041, Jan 1, 2013

Filed:

May 18, 2009

Appl. No.:

12/467962

Inventors:

Ransom H. Byers - Mountain View CA, US
Alexander E. Dillon - Cambridge MA, US
Thomas C. Kochem - Belmont MA, US
Daniel W. Rice - Gettysburg PA, US
Allison L. Schmidt - Dothan AL, US
Gary A. Jordan - Litchfield NH, US
Douglas Pleskow - Needham MA, US
Brian Tinkham - South Boston MA, US

Assignee:

Boston Scientific Scimed, Inc. - Maple Grove MN

International Classification:

A61B 1/00
A61B 1/12
A61M 5/178
A61M 5/14

US Classification:

600154, 600159, 60416701, 60416706, 604256

Abstract:

Endoscope assemblies, biopsy caps, and methods for making and using the same. An example endoscope assembly may include an endoscope having a channel formed therein and a port that provides access to the channel. A cap may be coupled to the port. The cap may include a base having a securing member for securing the cap to the port, an outer shell, a locking member coupled to the outer shell, an inner seal member, and a central opening that extends to the channel. The inner seal member may include a plurality of flaps.