Daniel C Robbins

US Patent:

58088628, Sep 15, 1998

Filed:

Mar 30, 1994

Appl. No.:

8/220406

Inventors:

Daniel C. Robbins - Easley SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 116

US Classification:

361681

Abstract:

A convertible computer includes a base portion having an operative side and a rear side. The computer further includes a display portion, pivotally attached to the base portion, having an operative side and a rear side, the rear side of the display portion being positionable substantially adjacent the rear side of the base portion. Moreover, the computer includes a cover positionable over the operative side of the base portion.

US Patent:

50291912, Jul 2, 1991

Filed:

Jan 29, 1990

Appl. No.:

7/471562

Inventors:

Daniel C. Robbins - Tucson AZ

Assignee:

Allied-Signal Inc. - Morris Township, Morris County NJ

International Classification:

H03K 2102
H03K 2139

US Classification:

377110

Abstract:

A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).

US Patent:

53275403, Jul 5, 1994

Filed:

Feb 1, 1993

Appl. No.:

8/016652

Inventors:

Thomas F. Heil - Easley SC
Daniel C. Robbins - Easley SC
Edward A. McDonald - Lexington SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 13362

US Classification:

395325

Abstract:

A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.

US Patent:

60555831, Apr 25, 2000

Filed:

Mar 27, 1997

Appl. No.:

8/828780

Inventors:

Daniel C. Robbins - Durham NC

Assignee:

Mitsubishi Semiconductor America, Inc. - Durham NC

International Classification:

G06F 1200

US Classification:

710 22

Abstract:

A device driver initiates a DMA transfer and repeatedly reads a semaphore from a specified location in system memory. Upon completion of a DMA transfer, a DMA controller writes a semaphore containing status information to the specified location in system memory, informing the device driver that the DMA transfer is completed. A cache memory for the specified location in system memory is provided to further reduce the latency between DMA transfers.

US Patent:

63238454, Nov 27, 2001

Filed:

Mar 6, 1995

Appl. No.:

8/398834

Inventors:

Daniel C. Robbins - Durham NC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G09G 500

US Classification:

345168

Abstract:

A computer 10 has an input device 12 keyboard with two sets of input keys 14, 16 separated by a touch pad 20. The touch pad 20 is accessed by an operator's index finger from the home row of keys, typically the next to last row.

US Patent:

53597150, Oct 25, 1994

Filed:

Sep 16, 1991

Appl. No.:

7/760786

Inventors:

Thomas F. Heil - Easley SC
Craig A. Walrath - Easley SC
Jimmy D. Pike - Columbia SC
Edward A. McDonald - Lexington SC
Arthur F. Cochcroft - West Columbia SC
P. Chris Raeuber - Central SC
Daniel C. Robbins - Easley SC
Gene F. Young - Lexington SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

395325

Abstract:

Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.