Daniel A Simon

US Patent:

7149801, Dec 12, 2006

Filed:

Nov 8, 2002

Appl. No.:

10/290879

Inventors:

Michael Burrows - Palo Alto CA, US
Martin Abadi - Palo Alto CA, US
Mark Steven Manasse - San Francisco CA, US
Edward P. Wobber - Menlo Park CA, US
Daniel Ron Simon - Redmond WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 15/173
H04K 1/00

US Classification:

709225, 713201, 380 28

Abstract:

A resource may be abused if its users incur little or no cost. For example, e-mail abuse is rampant because sending an e-mail has negligible cost for the sender. Such abuse may be discouraged by introducing an artificial cost in the form of a moderately expensive computation. Thus, the sender of an e-mail might be required to pay by computing for a few seconds before the e-mail is accepted. Unfortunately, because of sharp disparities across computer systems, this approach may be ineffective against malicious users with high-end systems, prohibitively slow for legitimate users with low-end systems, or both. Starting from this observation, we identify moderately hard, memory bound functions that most recent computer systems will evaluate at about the same speed, and we explain how to use them for protecting against abuses.

US Patent:

20020127763, Sep 12, 2002

Filed:

Dec 28, 2000

Appl. No.:

09/752798

Inventors:

Mohamed Arafa - Chandler AR, US
Weimin Han - Portland OR, US
Alan Myers - Portland OR, US
Daniel Simon - Hillsboro OR, US

International Classification:

H01L021/00

US Classification:

438/076000

Abstract:

L-shaped spacers for use adjacent to the vertical sidewalls of gate electrodes in the manufacture of MOS integrated circuits are described along with methods of fabricating such structures that do not require any additional cost compared to conventional manufacturing processes. A spacer is formed as a tri-layer of silicon oxide/silicon nitride/silicon oxide deposited in- situ at low temperature using a conventional furnace and a bis(tertiarybutylamino) silane chemistry deposition. The spacer has the same performance as a conventional spacer during deep source/drain (S/D) implants. Prior to a cleaning operation which precedes silicidation, the top oxide layer is removed leading to improved gap-fill characteristics. The upper oxide may to removed before deep S/D implantation to further achieve reduction of series resistance.

US Patent:

20070239760, Oct 11, 2007

Filed:

Apr 9, 2006

Appl. No.:

11/279108

Inventors:

Daniel Simon - Santa Clara CA, US

International Classification:

G06F 7/00

US Classification:

707102000

Abstract:

An Internet based computer application that consists of a back-end user interface for use by the client (“client”), and a front-end interface website for use by the end-user of the client (“user”, “end-user”), comprising customisable frequently asked questions (FAQs), help pages, discussion forums, downloadable documents, user created web pages, multiple word and phrase searching, query bot natural language parser, news and event ticker, and a customisable calendar. The front end is accessed by the end-user via a unique website address, and allows them access to the aforementioned features. The back end is accessed by the client using a unique username and password, and allows the client to modify all aforementioned features, an image library, account information, and other website features. All user-accessible features provide information to the user and provide feedback to the client, allowing them to adapt their website to the specific needs of their end-users.

US Patent:

20220254045, Aug 11, 2022

Filed:

Feb 2, 2022

Appl. No.:

17/591515

Inventors:

- Redmond WA, US
Jared S. Heinly - Durham NC, US
Srinivas Kapaganty - Suwanee GA, US
Daniel B. Simon - Portland OR, US
Brooke N. Steele - Ferguson NC, US

International Classification:

G06T 7/55
G06T 17/00
H04N 5/232
G06T 7/246
G06T 7/00

Abstract:

Techniques are described for automated analysis and use of data acquired about an object of interest, such as from a physically mounted camera or other sensing device with only partial coverage of the object exterior, such as to automatically generate a computer model of the object from visual data in images and to use the computer model to automatically estimate values for one or more object attributes. For example, the described techniques may be used to measure the volume of a pile of material significantly larger than a human using images acquired by one or more fixed-location cameras that provide visual coverage of only a subset of the pile's exterior. The images from such physically mounted devices may be acquired at various times (e.g., when triggered by conditions in the environment of the object, dynamically upon request, etc.), and may be used to monitor changes in the object.

US Patent:

20190393105, Dec 26, 2019

Filed:

Jun 21, 2018

Appl. No.:

16/015096

Inventors:

- Fremont CA, US
Daniel Anthony Simon - San Jose CA, US

International Classification:

H01L 21/66
H01L 21/027
H01L 21/02
G03F 7/16
C23C 16/40
C23C 16/455

Abstract:

Photoresist features can be characterized by electron microscopy-based metrology. A protective coating may be deposited on the photoresist with no change or minimal change to the dimensions of the underlying photoresist features, where the protective coating may be conformal and formed in a reactor operated under low temperature and low plasma conditions. In some implementations, the protective coating is formed by plasma-enhanced atomic layer deposition. Reliable and accurate profile information of photoresist features can be captured by metrology using the protective coating.

US Patent:

20170053998, Feb 23, 2017

Filed:

Mar 24, 2014

Appl. No.:

15/118838

Inventors:

- Santa Clara CA, US
Daniel A. SIMON - Hillsboro OR, US
Kelin J. KUHN - Aloha OR, US
Curtis W. WARD - Hillsboro OR, US

International Classification:

H01L 29/66
H01L 29/423
H01L 29/786
H01L 29/06

Abstract:

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.

US Patent:

20170047452, Feb 16, 2017

Filed:

Oct 26, 2016

Appl. No.:

15/335269

Inventors:

- Santa Clara CA, US
Daniel A. Simon - Hillsboro OR, US
Nadia M. Rahhal-Orabi - Hillsboro OR, US
Chul-Hyun Lim - Portland OR, US
Kelin J. Kuhn - Aloha OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 29/786
H01L 21/8238
H01L 29/66
H01L 27/092
H01L 29/06
H01L 29/423

Abstract:

A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

US Patent:

20160211322, Jul 21, 2016

Filed:

Oct 3, 2013

Appl. No.:

14/916093

Inventors:

- Santa Clara CA, US
Daniel A. SIMON - Hillsboro OR, US
Nadia M. RAHHAL-ORABI - Hillsboro OR, US
Chul-Hyun LIM - Portland OR, US
Kelin J. KUHN - Aloha OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 29/06
H01L 29/161
H01L 29/423
H01L 29/66

Abstract:

A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.