Daniel C Skinner

US Patent:

62292188, May 8, 2001

Filed:

Nov 6, 1998

Appl. No.:

9/187477

Inventors:

William J. Casey - Meridian ID
Andrew J. Heidelberg - Boise ID
Daniel C. Skinner - Boise ID

Assignee:

MCMS, Inc. - Nampa ID

International Classification:

H01L 2348

US Classification:

257778

Abstract:

An interconnect device for connecting an electronic package, whether it be a single chip or a multi-component device, to a primary substrate requiring the mating of dissimilar solder patterns includes a secondary substrate having a first face and a second face. The first face of the secondary substrate may include a first pattern of conductive lands formed on the first face corresponding to a plurality of conductive leads of an electronic package. The second face of the secondary substrate includes a second pattern of conductive lands corresponding to a plurality of conductive lands formed on the primary substrate. The first pattern of conductive lands formed on the first face is electrically connected to the second pattern of conductive lands formed on the second face via surface and internal conductive paths. Solder ball reflow soldering methods are used to connect the electronic device to the secondary substrate and to connect the secondary substrate to the primary substrate.

US Patent:

20230072539, Mar 9, 2023

Filed:

Jul 29, 2022

Appl. No.:

17/877724

Inventors:

- Boise ID, US
David Roberts - Meridian ID, US
Russell B. Lloyd - Boise ID, US
William Tiffany - Eagle ID, US
Jeffery Tanner - Meridian ID, US
Terrence Leslie - Reva VA, US
Daniel Skinner - Meridian ID, US
Indranil Roy - Boise ID, US

International Classification:

G06N 3/063
G06K 9/62
G06F 9/38

Abstract:

Introduced here is an artificial intelligence system designed for machine learning. The system may be based on a neuromorphic computational model that learns spatial patterns in inputs using data structures called Sparse Distributed Representations (SDRs) to represent the inputs. Moreover, the system can generate signatures for these SDRs, and these signatures may be used to create definitions of classes or subclasses for classification purposes.

US Patent:

20210287724, Sep 16, 2021

Filed:

Apr 6, 2021

Appl. No.:

17/301531

Inventors:

- Boise ID, US
Daniel C. Skinner - Meridian ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 7/10

Abstract:

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

US Patent:

20200312387, Oct 1, 2020

Filed:

Apr 21, 2020

Appl. No.:

16/853917

Inventors:

- BOISE ID, US
Daniel C. Skinner - Meridian ID, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G11C 7/10

Abstract:

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

US Patent:

20190341085, Nov 7, 2019

Filed:

Jul 16, 2019

Appl. No.:

16/513431

Inventors:

- Boise ID, US
Daniel C. Skinner - Meridian ID, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G11C 7/10

Abstract:

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

US Patent:

20190027208, Jan 24, 2019

Filed:

Sep 21, 2018

Appl. No.:

16/138621

Inventors:

- Boise ID, US
Moo Sung Chae - Boise ID, US
Daniel Skinner - Meridian ID, US

International Classification:

G11C 11/4076
G11C 7/22
G11C 11/4093
G11C 11/4096
G11C 7/06
G11C 7/10
G11C 7/14

Abstract:

A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

US Patent:

20180211695, Jul 26, 2018

Filed:

Mar 22, 2018

Appl. No.:

15/933167

Inventors:

- Boise ID, US
Daniel C. Skinner - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/10

Abstract:

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

US Patent:

20170133080, May 11, 2017

Filed:

Jan 25, 2017

Appl. No.:

15/415655

Inventors:

- BOISE ID, US
MOO SUNG CHAE - BOISE ID, US
DANIEL SKINNER - MERIDIAN ID, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G11C 11/4076
G11C 11/4093
G11C 11/4096

Abstract:

A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.