Danny J Neal

US Patent:

6347349, Feb 12, 2002

Filed:

Dec 28, 1998

Appl. No.:

09/221936

Inventors:

Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1314

US Classification:

710 62, 710100, 710112, 710128, 711117

Abstract:

An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.

US Patent:

6351784, Feb 26, 2002

Filed:

Dec 28, 1998

Appl. No.:

09/221930

Inventors:

Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1314

US Classification:

710128, 710108, 710112, 710129

Abstract:

An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.

US Patent:

6418497, Jul 9, 2002

Filed:

Dec 21, 1998

Appl. No.:

09/224119

Inventors:

Guy Lynn Guthrie - Austin TX
Richard Allen Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 948

US Classification:

710264, 710 48

Abstract:

A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

US Patent:

6493779, Dec 10, 2002

Filed:

Dec 21, 1998

Appl. No.:

09/224111

Inventors:

Guy Lynn Guthrie - Austin TX
Richard Allen Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1324

US Classification:

710260, 710263, 710264, 710 48

Abstract:

A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

US Patent:

6523140, Feb 18, 2003

Filed:

Oct 7, 1999

Appl. No.:

09/414337

Inventors:

Richard Louis Arndt - Austin TX
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 305

US Classification:

714 44, 714 43

Abstract:

A method and implementing computer system is provided in which specific device identification information is acquired when a faulty condition is detected during an information transfer transaction, and the condition is reported to the device driver of the identified device for corrective action without initiating a system shut-down. In one example, PCI adapter sequence information, including tag number, requester bus number, requester device number and requester function number is captured and used in reporting an error condition in order to identify and isolate the adapter in a recovery operation.

US Patent:

6581129, Jun 17, 2003

Filed:

Oct 7, 1999

Appl. No.:

09/414339

Inventors:

Pat Allen Buckland - Austin TX
Daniel Frank Moertl - Rochester MN
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX
Scott Michael Willenborg - Stewartville MN
Curtis Carl Wollbrink - Rochester MN
Adalberto Guillermo Yanes - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1336

US Classification:

710306, 710311, 710312, 710313

Abstract:

A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

US Patent:

6636947, Oct 21, 2003

Filed:

Aug 24, 2000

Appl. No.:

09/645177

Inventors:

Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1212

US Classification:

711141, 711144, 711145, 710306, 710312, 710313

Abstract:

A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.

US Patent:

6665782, Dec 16, 2003

Filed:

Aug 16, 2001

Appl. No.:

09/931430

Inventors:

Scott Leonard Daniels - Cedar Park TX
Danny Marvin Neal - Round Rock TX
Yat Hung Ng - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711163, 711115

Abstract:

A method and apparatus for preventing unauthorized access to data stored in memory utilizing two programmable logic devices as front end interfaces for the memory device and the data processing device which is to utilize the memory device, respectively. The two programmable logic devices are complementary programmed such that the signal lines between the data processing device and the memory core and/or their timing are scrambled at the interface between the two programmable logic devices, but are properly ordered with the proper timing at the interface between the memory core and the first programmable logic device and the interface between the data processing device and the second programmable logic device.