Danny M Neal

US Patent:

6347349, Feb 12, 2002

Filed:

Dec 28, 1998

Appl. No.:

09/221936

Inventors:

Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1314

US Classification:

710 62, 710100, 710112, 710128, 711117

Abstract:

An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.

US Patent:

6351784, Feb 26, 2002

Filed:

Dec 28, 1998

Appl. No.:

09/221930

Inventors:

Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1314

US Classification:

710128, 710108, 710112, 710129

Abstract:

An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.

US Patent:

6405276, Jun 11, 2002

Filed:

Dec 10, 1998

Appl. No.:

09/210135

Inventors:

Richard A. Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1338

US Classification:

710310, 710 57, 710109, 710306

Abstract:

A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor. The bridge is configured, in one embodiment, such that the pulling of posted memory write transactions in the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected in response to the read request. The invention further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge as described coupled between the host bus and a secondary bus.

US Patent:

6418497, Jul 9, 2002

Filed:

Dec 21, 1998

Appl. No.:

09/224119

Inventors:

Guy Lynn Guthrie - Austin TX
Richard Allen Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 948

US Classification:

710264, 710 48

Abstract:

A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

US Patent:

6418503, Jul 9, 2002

Filed:

Aug 19, 1999

Appl. No.:

09/377633

Inventors:

Daniel Frank Moertl - Rochester MN
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX
Adalberto Guillermo Yanes - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1310

US Classification:

710310, 710 52, 710 53, 710 55, 710 57

Abstract:

A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance. Transaction ordering rules are also implemented along with the arbiters to enable optimal information transfer management through the buffers, and routing tables are used to enable the addressing of all of the adapters on the plurality of PCI busses, and the efficient parallel peer-to-peer and IOP transfer of information between the adapter devices and also between the system and adapter devices on the PCI busses.

US Patent:

6421756, Jul 16, 2002

Filed:

May 6, 1999

Appl. No.:

09/306200

Inventors:

Richard A. Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1340

US Classification:

710310, 710 56

Abstract:

A method and implementing computer system are provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to adapter devices as needed during information transfers. In an exemplary peripheral component interconnect (PCI) system embodiment, a PCI Host Bridge (PHB) is coupled to a first PCI bus and one of the devices of the first PCI bus is occupied by a PCI-PCI bridge (PPB) which couples the first PCI bus to a second PCI bus. An assignment of PHB buffers in the PHB is made relative to the number of PCI devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically reassigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.

US Patent:

6425024, Jul 23, 2002

Filed:

May 18, 1999

Appl. No.:

09/314044

Inventors:

Richard Allen Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Lawrence Dean Whitley - Rochester MN
Adalberto Guillermo Yanes - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300

US Classification:

710 56, 711154

Abstract:

Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.

US Patent:

6457077, Sep 24, 2002

Filed:

Jun 10, 1999

Appl. No.:

09/329459

Inventors:

Richard A. Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Steven Mark Thurber - Austin TX
Adalberto Guillermo Yanes - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

710 56, 710100, 714 47

Abstract:

A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuits current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.