Darrell V Irvin

Deceased

from Portland, OR

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Also known as:

Darrell Irvin

Connected to:

Darrell Irvin Phones & Addresses

Portland, OR
Dallas, OR

Work

Company:

Northwest logic
Dec 2011 to Apr 2016
Position:

Senior logic designer

Education

Degree:

Master of Science, Masters
School / High School:

Montana State University - Bozeman
1974 to 1976
Specialities:

Electrical Engineering

Skills

Xilinx • Modelsim • Verilog • Fpga • Altera • Rtl Design • Quartus • Altera Quartus • Rtl Coding • Digital Design • Hardware Design • Vcs • Timing Closure • Hardware • Integrated Circuit Design • Microcontrollers • Embedded Systems • Vhdl • Debugging • Hardware Architecture • Pcb Design • Asic • Digital Signal Processors • Microprocessors • Simulations • Testing • Logic Design • Xilinx Ise • Embedded Software • Analog • Systemverilog • System Design • Processors • Firmware • Analog Circuit Design • Eda • Soc • Semiconductors • Schematic Capture • Perl • System Architecture • Device Drivers • Rtos • Open Verification Methodology • Static Timing Analysis • Oscilloscope • Tcl

Industries

Computer Hardware

Resumes

Darrell Boots Irvin

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Location:

Portland, OR

Industry:

Computer Hardware

Work:

Northwest Logic Dec 2011 - Apr 2016
Senior Logic Designer
Intel Corporation Jul 2010 - Sep 2011
Contract Rtl Designer
Grass Valley, A Belden Brand 1998 - Apr 2010
Principal Engineer
Tektronix 1976 - 1998
Engineer To Principal Engineer

Education:

Montana State University - Bozeman 1974 - 1976
Master of Science, Masters, Electrical Engineering Montana State University - Bozeman 1969 - 1973
Bachelors, Bachelor of Science, Electrical Engineering

Skills:

Xilinx
Modelsim
Verilog
Fpga
Altera
Rtl Design
Quartus
Altera Quartus
Rtl Coding
Digital Design
Hardware Design
Vcs
Timing Closure
Hardware
Integrated Circuit Design
Microcontrollers
Embedded Systems
Vhdl
Debugging
Hardware Architecture
Pcb Design
Asic
Digital Signal Processors
Microprocessors
Simulations
Testing
Logic Design
Xilinx Ise
Embedded Software
Analog
Systemverilog
System Design
Processors
Firmware
Analog Circuit Design
Eda
Soc
Semiconductors
Schematic Capture
Perl
System Architecture
Device Drivers
Rtos
Open Verification Methodology
Static Timing Analysis
Oscilloscope
Tcl

Us Patents

Method Of Low Cost Self-Test In A Video Display System System
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US Patent:

47729481, Sep 20, 1988
Filed:

Oct 26, 1987
Appl. No.:

7/113590
Inventors:

Darrell B. Irvin - Tigard OR
Assignee:

Tektronix, Inc. - Beaverton OR
International Classification:

H04N 1704
US Classification:

358139
Abstract:

In a color graphics display system, video analog self-test hardware for testing the system elements between the frame buffer and the CRT display monitor is provided including a bi-directional data bus between the graphics processor and the color map, an analog comparator, an integrator, and an analog multiplexor. The self-test method includes calibrating the self-test circuitry with respect to a reference voltage. The method next includes testing the DACs by outputting predetermined bit patterns to each of the DACs via the frame buffer, measuring each DAC output level in response to each input bit pattern, comparing the DAC output levels to predetermined limits, and reporting the results. Provision is made also for testing the system clock.

Method And Apparatus For Generating Phase Locked Digital Clock Signals
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US Patent:

45624020, Dec 31, 1985
Filed:

Apr 29, 1983
Appl. No.:

6/489978
Inventors:

Darrell B. Irvin - Tualatin OR
Assignee:

Tektronix, Inc. - Beaverton OR
International Classification:

H03K 117
H03K 513
H03K 2136
US Classification:

328 63
Abstract:

A method and apparatus for generating two phase locked digital clocks of different word rates particularly suited for a graphic and alphanumeric computer display terminal. Master and slave clock generators are used to generate output pulses at every N-th and M-th clocks of a common clock. A phase lock loop including the master clock generator and a phase lock counter dividing the common clock by the factor of the least common multiple of N and M is used to synchronize the slave clock generator.