Darren L Rust

US Patent:

7065424, Jun 20, 2006

Filed:

Mar 4, 2004

Appl. No.:

10/794796

Inventors:

William MacDonald - Mansfield TX, US
George Logsdon - Arlington TX, US
Darren Lee Rust - Arlington TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

700109, 700121, 702 84

Abstract:

This invention introduces systems and methods that control production process quality, wherein the production process has a plurality of durable items, each durable item is associated with a re-qualification process initiated as a function of a life expectancy associated therewith. The life expectancy associated with each durable item is reset upon completion of the associated re-qualification process. An exemplary method comprises (I) monitoring re-qualification indicia associated with each associated re-qualification process, and (ii) controlling availability of re-qualified durable items of the production process as a function of the re-qualification indicia to thereby control production process quality.

US Patent:

7470594, Dec 30, 2008

Filed:

Dec 14, 2005

Appl. No.:

11/302920

Inventors:

William Max Coppock - Arlington TX, US
Darren Lee Rust - Arlington TX, US
Charles A. Dark - Arlington TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/331
H01L 21/8222

US Classification:

438309, 438663, 438202, 438513, 438905, 257E21227, 257E21284, 257E21412, 257E21497

Abstract:

A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.

US Patent:

7043317, May 9, 2006

Filed:

Oct 30, 2003

Appl. No.:

10/698007

Inventors:

Darren Lee Rust - Arlington TX, US
George W. Logsdon - Arlington TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 19/00
H01H 43/00

US Classification:

700 99, 700121, 700306

Abstract:

A system and method is disclosed for monitoring each of a plurality of furnaces in a furnace process in semiconductor wafer fabrication. A furnace that is left open too long will absorb moisture from the atmosphere and should not be used for a furnace task. The system of the invention comprises a furnace resource allocator that comprises a furnace idle timer unit that keeps track of how long each furnace has been open. If the idle time for a selected furnace exceeds a predetermined limit, that furnace is rejected and another furnace is selected for use. Each furnace that is rejected is subjected to a furnace cycle purge process to remove moisture from the furnace so that the furnace may again be available for use.