Darryl W Walker

US Patent:

6384439, May 7, 2002

Filed:

Feb 1, 1999

Appl. No.:

09/241267

Inventors:

Darryl Walker - San Jose CA

Assignee:

Texas Instruments, Inc. - TX

International Classification:

H01L 27108

US Classification:

257296, 306401, 306623

Abstract:

A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM cell ( ) includes a storage capacitor ( ) and a pass transistor ( ). The pass transistor ( ) is formed within a silicon mesa ( ), and includes a source region ( ), drain region ( ) and channel region ( ). The channel region ( ) is formed below a furrow ( ) that is inset with respect to the top surface of the silicon mesa ( ). The channel region ( ) has a smaller thickness than that of the source region ( ) and drain region ( ). A top gate ( ) is disposed over the channel region ( ). Due to the reduced thickness channel region ( ), greater control of the operation of the pass transistor ( ) is provided, including an off state with reduced source-to-drain leakage. The greater thickness of the source region ( ) and drain region ( ) (relative to the channel region ( )) provides greater immunity to the adverse effects of contact spiking.

US Patent:

6661699, Dec 9, 2003

Filed:

Apr 11, 2000

Appl. No.:

09/546747

Inventors:

Darryl Gene Walker - San Jose CA 95135

International Classification:

G11C 1124

US Classification:

365149, 257 71, 257296, 257297, 257306, 257311

Abstract:

A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( ) includes a storage capacitor ( ) and a pass transistor ( ). The pass transistor ( ) includes a source region ( ), drain region ( ) and channel region ( ). A top gate ( ) is disposed over the channel region ( ) and a bottom gate ( ) is disposed below the channel region ( ). The top gate ( ) and bottom gate ( ) are commonly driven to provide greater control of the pass transistor ( ) operation, including an off state with reduced source-to-drain leakage. The DRAM array ( ) includes memory cells ( ) having pass transistors ( ) with double-gate structures. Memory cells ( ) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer ( ). The DRAM array ( ) further includes a strapping area that is void of memory cells.

US Patent:

6661702, Dec 9, 2003

Filed:

Jan 24, 2003

Appl. No.:

10/350653

Inventors:

Darryl Gene Walker - San Jose CA 95135

International Classification:

G11C 1124

US Classification:

365149, 251 71, 251297, 251296, 251306, 251311

Abstract:

A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( ) includes a storage capacitor ( ) and a pass transistor ( ). The pass transistor ( ) includes a source region ( ), drain region ( ) and channel region ( ). A top gate ( ) is disposed over the channel region ( ) and a bottom gate ( ) is disposed below the channel region ( ). The top gate ( ) and bottom gate ( ) are commonly driven to provide greater control of the pass transistor ( ) operation, including an off state with reduced source-to-drain leakage. The DRAM array ( ) includes memory cells ( ) having pass transistors ( ) with double-gate structures. Memory cells ( ) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer ( ). The DRAM array ( ) further includes a strapping area that is void of memory cells.

US Patent:

6934180, Aug 23, 2005

Filed:

Sep 29, 2003

Appl. No.:

10/675042

Inventors:

Darryl G. Walker - San Jose CA, US

International Classification:

G11C011/24

US Classification:

365149, 365222, 36523006, 257297, 257306, 257310

Abstract:

A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell () includes a storage capacitor () and a pass transistor (). The pass transistor () includes a source region (), drain region () and channel region (). A top gate () is disposed over the channel region () and a bottom gate () is disposed below the channel region (). The top gate () and bottom gate () are commonly driven to provide greater control of the pass transistor () operation, including an off state with reduced source-to-drain leakage. The DRAM array () includes memory cells () having pass transistors () with double-gate structures. Memory cells () within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (). The DRAM array () further includes a strapping area that is void of memory cells.

US Patent:

6967887, Nov 22, 2005

Filed:

Apr 26, 2004

Appl. No.:

10/832038

Inventors:

Darryl G. Walker - San Jose CA, US

International Classification:

G11C007/00
H01L027/108

US Classification:

365222, 365149, 36523006, 257297, 257296, 257306, 257311, 257907

Abstract:

A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell () includes a storage capacitor () and a pass transistor (). The pass transistor () includes a source region (), drain region () and channel region (). A top gate () is disposed over the channel region () and a bottom gate () is disposed below the channel region (). The top gate () and bottom gate () are commonly driven to provide greater control of the pass transistor () operation, including an off state with reduced source-to-drain leakage. The DRAM array () includes memory cells () having pass transistors () with double-gate structures. Memory cells () within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (). The DRAM array () further includes a strapping area that is void of memory cells.

US Patent:

7383149, Jun 3, 2008

Filed:

Dec 12, 2006

Appl. No.:

11/637280

Inventors:

Darryl Walker - San Jose CA, US

International Classification:

G06F 15/00

US Classification:

702130, 702127

Abstract:

A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

US Patent:

7480588, Jan 20, 2009

Filed:

Feb 20, 2007

Appl. No.:

11/708408

Inventors:

Darryl Walker - San Jose CA, US

International Classification:

G01K 1/08
G06F 15/00

US Classification:

702132

Abstract:

A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

US Patent:

7535786, May 19, 2009

Filed:

Feb 20, 2007

Appl. No.:

11/708185

Inventors:

Darryl Walker - San Jose CA, US

International Classification:

G11C 7/00

US Classification:

365222, 365211, 365226, 365227, 702130, 702132

Abstract:

The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.