Datong L Chen

US Patent:

6339248, Jan 15, 2002

Filed:

Nov 15, 1999

Appl. No.:

09/440481

Inventors:

Tiemin Zhao - Palo Alto CA
Xinping He - San Jose CA
Datong Chen - Fremont CA

Assignee:

Omnivision Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 3106

US Classification:

257461, 257233, 257291, 438 48, 438309

Abstract:

A photodiode with an optimized floating P+ region for a CMOS image sensor. The photodiode is constructed with a P+/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P+ floating region passivates the silicon surface to reduce dark currents. Unlike a traditional pinned photodiode structure, the P+ region in the present invention is not connected to the Pwell or Psub regions, thus making the P+ region floating. This avoids the addition of extra capacitance to the cell. The photodiode may be included as part of an active pixel sensor cell, the layout of which is fully compatible with the standard CMOS fabrication process. This type of active pixel sensor cell includes the photodiode, and may be configured with a three transistor configuration for reading out the photodiode signals. Examples of other configurations that the photodiode can be used with include two transistors, four transistors, log scale, as well as its ability to be used in a passive pixel implementation.

US Patent:

6365447, Apr 2, 2002

Filed:

Jan 12, 1998

Appl. No.:

09/005786

Inventors:

Datong Chen - Fremont CA
Reda Razouk - Sunnyvale CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 218238

US Classification:

438203, 438234, 438322, 438358

Abstract:

A method of making high voltage complementary bipolar and BiCMOS devices on a common substrate. The bipolar devices are vertical NPN and PNP transistors having the same structure. The fabrication process utilizes trench isolation and thus is scalable. The process uses two epitaxial silicon layers to form the high voltage NPN collector, with the PNP collector formed from a p-well diffused into the two epitaxial layers. The collector contact resistance is minimized by the use of sinker up/down structures formed at the interface of the two epitaxial layers. The process minimizes the thermal budget and therefore the up diffusion of the NPN and PNP buried layers. This maximizes the breakdown voltage at the collector-emitter junction for a given epitaxial thickness. The epitaxial layers may be doped as required depending upon the specifications for the high voltage NPN device. The process is compatible with the fabrication of low voltage devices, which can be formed by placing the sinker regions under the emitter region.

US Patent:

6404460, Jun 11, 2002

Filed:

Feb 19, 1999

Appl. No.:

09/252841

Inventors:

Datong Chen - Fremont CA
Xinping He - San Jose CA

Assignee:

Omnivision Technologies, Inc. - Sunnyvale CA

International Classification:

H04N 5208

US Classification:

348606, 348627

Abstract:

The present invention is directed to a method and apparatus for image edge enhancement with background noise reduction. According to the method and apparatus, background noise is reduced through use of feed forward gain control and threshold control of a sharpness control amplifier. In a prior art circuit, the sharpness control amplifier was controlled only by a sharpness control signal. By controlling the sharpness control amplifier also with a feed forward gain control and a threshold control, the circuit can be made to have background noise reduction while maintaining a continuous input/output characteristic curve. According to the input/output characteristic curve, when the amplitude of the transitions of the video signal are below a particular threshold value, the amplification of the sharpness control amplifier is reduced by the gain control, such that low amplitude noise signals are reduced. When the amplitude of the transitions of the video signal, representing image edge transitions, are above the amplitude of the threshold level, then normal signal amplification is produced. In this manner, the edges of the image are enhanced while background noise is reduced.

US Patent:

6441866, Aug 27, 2002

Filed:

Jan 14, 1999

Appl. No.:

09/231932

Inventors:

Datong Chen - Fremont CA
Hongli Yang - Sunnyvale CA

Assignee:

OmniVision Technologies, Inc. - Sunnyvale CA

International Classification:

H04N 521

US Classification:

348606, 348252

Abstract:

In the field of imaging, various components may contribute to a loss in resolution at higher spatial frequencies, both horizontally and vertically. Higher spatial frequencies may occur at the edge of an image, where there may be a large transition in the signal output between adjacent pixels. To compensate, an edge enhancement method that produces overshoots in the transitions of the video image signal is used. One of the problems with the edge enhancement method is that the noise in the input signal may not be adequately suppressed. To suppress the background noise in the video image signal while still performing the desired edge enhancement function, biasing circuitry may be used to suppress the smaller transitions in the input signal. In particular, the biasing circuitry may be placed in the signal path between the output of a first delay line and the noninverting inputs of two of the signal amplifiers. In this manner, the smaller transitions in the signal which represent background noise may be suppressed, while the edges of the video image signal are still enhanced.

US Patent:

6486521, Nov 26, 2002

Filed:

Oct 2, 2001

Appl. No.:

09/969920

Inventors:

Tiemin Zhao - Palo Alto CA
Xinping He - San Jose CA
Datong Chen - Fremont CA

Assignee:

OmniVision Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 3100

US Classification:

257443, 257461, 257463, 257292, 438 48, 438 66, 438 67, 438 73, 438 80, 438 87

Abstract:

A photodiode with an optimized floating P+ region for a CMOS image sensor. The photodiode is constructed with a P+/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P+ floating region passivates the silicon surface to reduce dark currents. Unlike a traditional pinned photodiode structure, the P+ region in the present invention is not connected to the Pwell or Psub regions, thus making the P+ region floating. This avoids the addition of extra capacitance to the cell. The photodiode may be included as part of an active pixel sensor cell, the layout of which is fully compatible with the standard CMOS fabrication process. This type of active pixel sensor cell includes the photodiode, and may be configured with a three transistor configuration for reading out the photodiode signals. Examples of other configurations that the photodiode can be used with include two transistors, four transistors, log scale, as well as its ability to be used in a passive pixel implementation.

US Patent:

6580849, Jun 17, 2003

Filed:

Jan 5, 2001

Appl. No.:

09/755526

Inventors:

Datong Chen - Sunnyvale CA
John C. Philipp - Sonoma CA
Ian Hardcastle - Sunnyvale CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G02B 626

US Classification:

385 18, 385 15, 385 16, 385 17, 385 25

Abstract:

An optical switch that includes optical paths organized into a set of M input optical paths and a set of N output optical paths. The optical switch additionally includes a faceted mirror corresponding to each of the M input optical paths and including N facets and a faceted mirror corresponding to each of the N output optical paths and including M facets. Finally, the optical switch includes a moving mechanism coupled to each faceted mirror to step the faceted mirror to selectively align one of the facets of the faceted mirror with the one of the optical paths with which the faceted mirror is associated. The facets of each of the faceted mirrors corresponding to one of the sets of optical paths, i. e. , the set of input optical paths or the set of output optical paths, are preferably angled to reflect light towards a different one of the faceted mirrors corresponding to the other of the sets of optical paths, i. e. , the set of output optical paths or the set of input optical paths, respectively.

US Patent:

6707496, Mar 16, 2004

Filed:

Sep 15, 1999

Appl. No.:

09/397634

Inventors:

Hongli Yang - Sunnyvale CA
Xinping He - San Jose CA
Datong Chen - Fremont CA

Assignee:

OmniVision Technologies, Inc. - Sunnyvale CA

International Classification:

H04N 314

US Classification:

348303, 348304

Abstract:

The present invention is directed to an analog delay line for a color CMOS image sensor which is compatible with MOS fabrication technology. The invention allows for the simultaneous reading of pixel signals from two rows of pixels so that combinations of signals from pixels in different rows may be obtained. The delay line includes a set of storage capacitors on which the pixel signals are stored, and a means for writing the signals from the pixels onto the capacitors in sequence. The stored analog pixel signals may then be read out from the delay line at the appropriate time so that they may be combined with pixel signals from adjacent pixels in different rows. In one embodiment, two delay lines are used, so that pixel signals from a current row can be written into one delay line, while the pixel signals from a previous row are being read out from the other delay line. In another embodiment, a single delay line is used in combination with a single pixel delay circuit. When the single pixel delay circuit is used, the pixel signals from a previous row are read out from the delay line and temporarily stored in the single pixel delay circuit, one at a time, shortly after which the pixel signals from the next row are written into the delay line.

US Patent:

6727946, Apr 27, 2004

Filed:

Dec 14, 1999

Appl. No.:

09/461668

Inventors:

Tiemin Zhao - Palo Alto CA
Xinping He - San Jose CA
Qingwei Shan - Cupertino CA
Datong Chen - Fremont CA

Assignee:

OmniVision Technologies, Inc. - Sunnyvale CA

International Classification:

H04N 314

US Classification:

348308, 348310, 2502081

Abstract:

An improved active pixel sensor soft reset circuit for reducing image lag while maintaining low reset kTC noise. The circuit pulls down the sensor potential to a sufficiently low level before the soft reset function is completed. The level to which the sensor potential is pulled is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function begins. The timing of the pull down function is such that the sensor is stabilized at the low potential before the soft reset function completes. In one embodiment, the sensor potential is pulled down using a pull-down circuit, which may consist of a CMOS type inverter. In another embodiment, the sensor potential is pulled down by the bit line. Two ways in which the bit line may be pulled down are natural discharge, or by increasing the bias on the loading transistor. Two ways in which the bias on the loading transistor may be increased are a biasing circuit, or by using a pull-down transistor.