David B Addison

US Patent:

20170185563, Jun 29, 2017

Filed:

Dec 24, 2015

Appl. No.:

14/998255

Inventors:

- Santa Clara CA, US
Charles F. Giefer - Seattle WA, US
David Addison - Issaquah WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/173
G06F 9/48
G06F 3/06

Abstract:

Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.