David Ian Allison

US Patent:

6988266, Jan 17, 2006

Filed:

May 8, 2001

Appl. No.:

09/851018

Inventors:

William K. Lam - Newark CA, US
David S. Allison - San Ramon CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717160, 717161, 717150, 717151

Abstract:

A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

US Patent:

7043596, May 9, 2006

Filed:

Mar 29, 2002

Appl. No.:

10/113060

Inventors:

Thomas M. McWilliams - Menlo Park CA, US
Jeffrey B. Rubin - Pleasanton CA, US
Michael W. Parkin - Palo Alto CA, US
Oyekunle A. Olukotun - Stanford CA, US
Derek E. Pappas - Union City CA, US
Jeffrey M. Broughton - Palo Alto CA, US
David R. Emberson - Santa Cruz CA, US
David S. Allison - San Ramon CA, US
Ashley N. Saulsbury - Los Gatos CA, US
Earl T. Cohen - Fremont CA, US
Nyles I. Nettleton - Campbell CA, US
James B. Burr - Foster City CA, US
Liang T. Chen - Saratoga CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 13/00
H04L 12/28

US Classification:

710317, 370351

Abstract:

A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

US Patent:

7162403, Jan 9, 2007

Filed:

Feb 14, 2003

Appl. No.:

10/366859

Inventors:

Nasser Nouri - San Jose CA, US
Ping-Chih Wu - Cupertino CA, US
Mohamed Soufi - Santa Clara CA, US
David S. Allison - San Ramon CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

703 14, 716 5

Abstract:

A system for tracing signals for a cycle-based simulation includes a traced signal and a system resources availability information of the cycle-based simulation, a runtime compiler configured to use the system resources availability information to assign a system resource to trace the traced signal, a logic design used with the system resources availability information to generate a simulation image, a first value of the traced signal generated by execution of a simulation image, and a traced signal buffer configured to store the first value and upload the first value.

US Patent:

7449184, Nov 11, 2008

Filed:

Jun 15, 2005

Appl. No.:

11/154091

Inventors:

David E. Allison - San Mateo CA, US
Rene Bruno - Marseilles, FR
Jian-Feng Lu - Foster City CA, US
Chee M. Ng - San Mateo CA, US

Assignee:

Genentech, Inc. - South San Francisco CA

International Classification:

A61K 39/365
C07K 16/30

US Classification:

4241381, 4241301, 4241411, 4241431, 5303871, 5303881, 5303888, 53038885, 514 2

Abstract:

The present invention concerns fixed dosing of HER antibodies, such as Pertuzumab.

US Patent:

8404234, Mar 26, 2013

Filed:

Oct 9, 2008

Appl. No.:

12/248223

Inventors:

David E. Allison - San Mateo CA, US
Rene Bruno - Marseilles, FR
Jian-Feng Lu - Foster City CA, US
Chee M. Ng - San Mateo CA, US

Assignee:

Genentech, Inc. - South San Francisco CA

International Classification:

A61K 39/395

US Classification:

4241381, 4241331, 4241411, 4241551

Abstract:

The present invention concerns fixed dosing of HER antibodies, such as Pertuzumab.

US Patent:

20130138836, May 30, 2013

Filed:

Aug 20, 2009

Appl. No.:

12/544744

Inventors:

Ariel Cohen - Cupertino CA, US
Ashok Krishnamurthi - Saratoga CA, US
Viswanath Krishnamurthy - Sunnyvale CA, US
Frank Salzmann - Danville CA, US
David S. Allison - San Ramon CA, US
Cheng Tang - Saratoga CA, US

Assignee:

Xsigo Systems - San Jose CA

International Classification:

G06F 15/16

US Classification:

709250

Abstract:

Provided is a novel approach for connecting servers to peripherals, such as NICs, HBAs, and SAS/SATA controllers. Also provided are methods of arranging peripherals within one or more I/O directors, which are connected to the servers over an Ethernet network. Such arrangement allows sharing the same resource among multiple servers.

US Patent:

40471950, Sep 6, 1977

Filed:

Sep 22, 1975

Appl. No.:

5/615465

Inventors:

David F. Allison - Los Altos CA

Assignee:

Scientific Micro Systems, Inc. - Sunnyvale CA

International Classification:

H01L 2906
H01L 2704
H01L 2712
H01L 2702

US Classification:

357 55

Abstract:

Semiconductor structure having a plurality of isolated islands in which semiconductor devices are formed and which are interconnected to form an integrated circuit. The islands are isolated from each other by a combination of dielectric isolation in the form of moats and regions of higher conductivity extending downwardly into the semiconductor body from the moats. The semiconductor body from which the semiconductor structure is formed has a surface with a orientation. An etch resistant mask is formed on the surface. An anisotropic etch is utilized to provide a plurality of isolation moats extending downwardly from the surface and having inclined side walls oriented along a crystal plane different from the plane and having bottom walls oriented along the crystal plane of the semiconductor body. The side walls and the bottom walls of the moats are oxidized. The oxide on the bottom walls is then removed.

US Patent:

42683483, May 19, 1981

Filed:

Aug 1, 1966

Appl. No.:

4/569368

Inventors:

David F. Allison - Palo Alto CA
David A. Maxwell - San Jose CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

H01L 2122
H01L 21304
H01L 21308

US Classification:

156645

Abstract:

1. In a method for forming a semiconductor structure utilizing a semiconductor body, forming a grid structure in the semiconductor body, forming a support structure upon the grid structure, removing only a portion of the semiconductor body to provide a semiconductor body which has a substantially uniform thickness in the vicinity of the grid structure and in which the grid structure does not intercept the exposed surface of the semiconductor body, and forming additional grid structure in the semiconductor body joining the first named grid structure so that islands of semiconductor material are formed in the semiconductor body which are isolated from each other and from the support structure. 23. In a method for forming a semiconductor structure utilizing a semiconductor body having a surface, forming a layer of insulating material on the surface of the semiconductor body, forming a recessed grid in the layer of insulating material and extending into the semiconductor body, forming a layer of insulating material on the recessed grid adhering to said surface and having a depth which is insufficient to fill the recessed grid to form a grid structure in a semiconductor body prior to the formation of a semiconductor device in the semiconductor body, forming a support structure upon the grid structure, removing a portion of the semiconductor body and diffusing isolation fences into the semiconductor body which extend and make contact with the layer of insulating material to form a plurality of islands of semiconductor material isolated from each other and from the support structure.