David R Armstrong

US Patent:

7137053, Nov 14, 2006

Filed:

Sep 4, 2001

Appl. No.:

09/946857

Inventors:

Ajay Khoche - Cupertino CA, US
Jochen Rivoir - Magstadt, DE
David H. Armstrong - Boulder CO, US

Assignee:

Verigg IPco - Singapore

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.

US Patent:

7788562, Aug 31, 2010

Filed:

Nov 29, 2006

Appl. No.:

11/606866

Inventors:

Thomas Joseph Brennan - Santa Clara CA, US
David Harry Armstrong - Santa Clara CA, US

Assignee:

Advantest Corporation - Tokyo, Nerima-Ku

International Classification:

G01R 31/28

US Classification:

714732, 714735

Abstract:

Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are not received. This allows fast/complex ATE Rx memory to be replaced by slower and smaller MISR pattern memory. At the end of a test period, the LFSRs or MISRs generate signatures which are then compared to a set of possible valid signatures for non-deterministic data. A pass/fail result is produced. By masking indeterminate states, fewer valid signatures need to be stored. Masking of the MISRs or LFSRs may be based on the fact that indeterminate states and good data in a serial output data stream tend to occur in predictable patterns, or that good data may follow alignment characters. MISR or LFSR output signatures may also be employed to test individual pattern segments instead of the entire input test pattern. This expected DUT Rx data compression implementation works for one signature (deterministic) data as well.

US Patent:

60657510, May 23, 2000

Filed:

Apr 30, 1998

Appl. No.:

9/070182

Inventors:

David Garvin Armstrong - Brunswick ME

International Classification:

A63F 300

US Classification:

273271

Abstract:

A retainer for the game of Go so configured that when the retainer is secured over a board on which a game is in progress, each stone on the board is constrained to remain in its proper position. Retention means are provided for holding the retainer and the playing board together reliably so that they can be moved about, placed on edge for storage, etc. , as may be convenient. Integral means are provided for indicating which side has the next turn, the color and the net number of the captured stones, and the intersection, if any, on which immediate play is forbidden because of an active "ko".

US Patent:

20190086468, Mar 21, 2019

Filed:

Sep 21, 2018

Appl. No.:

16/138029

Inventors:

- Tokyo, JP
DAVID ARMSTRONG - San Jose CA, US
JINLEI LIU - San Jose CA, US
TSE-KUN CHEN - San Jose CA, US

International Classification:

G01R 31/28
G01R 1/44

Abstract:

Automated test equipment can generate feed-forward temperature profile information for a device under test (DUT), where the temperature data is determined from measurements performed during execution of a test pattern on the DUT, and can synchronize the temperature data and the cycles of the test pattern.